Microchip Technology Inc.
ATSAM4CMS8C_0
2024.06.03
Atmel ATSAM4CMS8C Microcontroller
CM4
r0p0
selectable
true
4
false
8
32
ADC
Analog-to-Digital Converter
ADC
0x0
0x0
0x50
registers
n
ADC
29
ACR
Analog Control Register
0x94
32
read-write
n
0x0
0x0
FORCEREF
Force Internal Reference Voltage
19
1
read-write
IRVCE
Internal Reference Voltage Change Enable
2
1
read-write
STUCK_AT_DEFAULT
The internal reference voltage is stuck at the default value (see the Electrical Characteristics for further details).
0
SELECTION
The internal reference voltage is defined by field IRVS.
1
IRVS
Internal Reference Voltage Selection
3
4
read-write
ONREF
Internal Voltage Reference ON
20
1
read-write
CDR0
Channel Data Register
0x50
32
read-only
n
DATA
Converted Data
0
12
read-only
CDR1
Channel Data Register
0x54
32
read-only
n
DATA
Converted Data
0
12
read-only
CDR2
Channel Data Register
0x58
32
read-only
n
DATA
Converted Data
0
12
read-only
CDR3
Channel Data Register
0x5C
32
read-only
n
DATA
Converted Data
0
12
read-only
CDR4
Channel Data Register
0x60
32
read-only
n
DATA
Converted Data
0
12
read-only
CDR5
Channel Data Register
0x64
32
read-only
n
DATA
Converted Data
0
12
read-only
CDR6
Channel Data Register
0x68
32
read-only
n
DATA
Converted Data
0
12
read-only
CDR7
Channel Data Register
0x6C
32
read-only
n
DATA
Converted Data
0
12
read-only
CDR[0]
Channel Data Register
0xA0
32
read-only
n
0x0
0x0
DATA
Converted Data
0
12
read-only
CDR[1]
Channel Data Register
0xF4
32
read-only
n
0x0
0x0
DATA
Converted Data
0
12
read-only
CDR[2]
Channel Data Register
0x14C
32
read-only
n
0x0
0x0
DATA
Converted Data
0
12
read-only
CDR[3]
Channel Data Register
0x1A8
32
read-only
n
0x0
0x0
DATA
Converted Data
0
12
read-only
CDR[4]
Channel Data Register
0x208
32
read-only
n
0x0
0x0
DATA
Converted Data
0
12
read-only
CDR[5]
Channel Data Register
0x26C
32
read-only
n
0x0
0x0
DATA
Converted Data
0
12
read-only
CDR[6]
Channel Data Register
0x2D4
32
read-only
n
0x0
0x0
DATA
Converted Data
0
12
read-only
CDR[7]
Channel Data Register
0x340
32
read-only
n
0x0
0x0
DATA
Converted Data
0
12
read-only
CHDR
Channel Disable Register
0x14
32
write-only
n
0x0
0x0
CH0
Channel 0 Disable
0
1
write-only
CH1
Channel 1 Disable
1
1
write-only
CH2
Channel 2 Disable
2
1
write-only
CH3
Channel 3 Disable
3
1
write-only
CH6
Channel 6 Disable
6
1
write-only
CH7
Channel 7 Disable
7
1
write-only
CHER
Channel Enable Register
0x10
32
write-only
n
0x0
0x0
CH0
Channel 0 Enable
0
1
write-only
CH1
Channel 1 Enable
1
1
write-only
CH2
Channel 2 Enable
2
1
write-only
CH3
Channel 3 Enable
3
1
write-only
CH6
Channel 6 Enable
6
1
write-only
CH7
Channel 7 Enable
7
1
write-only
CHSR
Channel Status Register
0x18
32
read-only
n
0x0
0x0
CH0
Channel 0 Status
0
1
read-only
CH1
Channel 1 Status
1
1
read-only
CH2
Channel 2 Status
2
1
read-only
CH3
Channel 3 Status
3
1
read-only
CH6
Channel 6 Status
6
1
read-only
CH7
Channel 7 Status
7
1
read-only
CR
Control Register
0x0
32
write-only
n
0x0
0x0
START
Start Conversion
1
1
write-only
SWRST
Software Reset
0
1
write-only
CWR
Compare Window Register
0x44
32
read-write
n
0x0
0x0
HIGHTHRES
High Threshold
16
12
read-write
LOWTHRES
Low Threshold
0
12
read-write
EMR
Extended Mode Register
0x40
32
read-write
n
0x0
0x0
ASTE
Averaging on Single Trigger Event
20
1
read-write
MULTI_TRIG_AVERAGE
The average requests several trigger events.
0
SINGLE_TRIG_AVERAGE
The average requests only one trigger event.
1
CMPALL
Compare All Channels
9
1
read-write
CMPFILTER
Compare Event Filtering
12
2
read-write
CMPMODE
Comparison Mode
0
2
read-write
LOW
Generates an event when the converted data is lower than the low threshold of the window.
0x0
HIGH
Generates an event when the converted data is higher than the high threshold of the window.
0x1
IN
Generates an event when the converted data is in the comparison window.
0x2
OUT
Generates an event when the converted data is out of the comparison window.
0x3
CMPSEL
Comparison Selected Channel
4
4
read-write
OSR
Over Sampling Rate
16
2
read-write
NO_AVERAGE
No averaging. ADC sample rate is maximum.
0x0
OSR4
1-bit enhanced resolution by averaging. ADC sample rate divided by 4.
0x1
OSR16
2-bit enhanced resolution by averaging. ADC sample rate divided by 16.
0x2
TAG
TAG of the ADC_LDCR register
24
1
read-write
IDR
Interrupt Disable Register
0x28
32
write-only
n
0x0
0x0
COMPE
Comparison Event Interrupt Disable
26
1
write-only
DRDY
Data Ready Interrupt Disable
24
1
write-only
ENDRX
End of Receive Buffer Interrupt Disable
27
1
write-only
EOC0
End of Conversion Interrupt Disable 0
0
1
write-only
EOC1
End of Conversion Interrupt Disable 1
1
1
write-only
EOC2
End of Conversion Interrupt Disable 2
2
1
write-only
EOC3
End of Conversion Interrupt Disable 3
3
1
write-only
EOC6
End of Conversion Interrupt Disable 6
6
1
write-only
EOC7
End of Conversion Interrupt Disable 7
7
1
write-only
GOVRE
General Overrun Error Interrupt Disable
25
1
write-only
RXBUFF
Receive Buffer Full Interrupt Disable
28
1
write-only
TEMPCHG
Temperature Change Interrupt Disable
19
1
write-only
IER
Interrupt Enable Register
0x24
32
write-only
n
0x0
0x0
COMPE
Comparison Event Interrupt Enable
26
1
write-only
DRDY
Data Ready Interrupt Enable
24
1
write-only
ENDRX
End of Receive Buffer Interrupt Enable
27
1
write-only
EOC0
End of Conversion Interrupt Enable 0
0
1
write-only
EOC1
End of Conversion Interrupt Enable 1
1
1
write-only
EOC2
End of Conversion Interrupt Enable 2
2
1
write-only
EOC3
End of Conversion Interrupt Enable 3
3
1
write-only
EOC6
End of Conversion Interrupt Enable 6
6
1
write-only
EOC7
End of Conversion Interrupt Enable 7
7
1
write-only
GOVRE
General Overrun Error Interrupt Enable
25
1
write-only
RXBUFF
Receive Buffer Full Interrupt Enable
28
1
write-only
TEMPCHG
Temperature Change Interrupt Enable
19
1
write-only
IMR
Interrupt Mask Register
0x2C
32
read-only
n
0x0
0x0
COMPE
Comparison Event Interrupt Mask
26
1
read-only
DRDY
Data Ready Interrupt Mask
24
1
read-only
ENDRX
End of Receive Buffer Interrupt Mask
27
1
read-only
EOC0
End of Conversion Interrupt Mask 0
0
1
read-only
EOC1
End of Conversion Interrupt Mask 1
1
1
read-only
EOC2
End of Conversion Interrupt Mask 2
2
1
read-only
EOC3
End of Conversion Interrupt Mask 3
3
1
read-only
EOC6
End of Conversion Interrupt Mask 6
6
1
read-only
EOC7
End of Conversion Interrupt Mask 7
7
1
read-only
GOVRE
General Overrun Error Interrupt Mask
25
1
read-only
RXBUFF
Receive Buffer Full Interrupt Mask
28
1
read-only
TEMPCHG
Temperature Change Interrupt Mask
19
1
read-only
ISR
Interrupt Status Register
0x30
32
read-only
n
0x0
0x0
COMPE
Comparison Event (cleared on read)
26
1
read-only
DRDY
Data Ready (automatically set/cleared)
24
1
read-only
ENDRX
End of Receive Transfer (automatically set/cleared)
27
1
read-only
EOC0
End of Conversion 0 (automatically set/cleared)
0
1
read-only
EOC1
End of Conversion 1 (automatically set/cleared)
1
1
read-only
EOC2
End of Conversion 2 (automatically set/cleared)
2
1
read-only
EOC3
End of Conversion 3 (automatically set/cleared)
3
1
read-only
EOC6
End of Conversion 6 (automatically set/cleared)
6
1
read-only
EOC7
End of Conversion 7 (automatically set/cleared)
7
1
read-only
GOVRE
General Overrun Error (cleared on read)
25
1
read-only
RXBUFF
Receive Buffer Full (automatically set/cleared)
28
1
read-only
TEMPCHG
Temperature Change (cleared on read)
19
1
read-only
LCDR
Last Converted Data Register
0x20
32
read-only
n
0x0
0x0
CHNB
Channel Number
12
4
read-only
LDATA
Last Data Converted
0
12
read-only
MR
Mode Register
0x4
32
read-write
n
0x0
0x0
FREERUN
Free Run Mode
7
1
read-write
OFF
Normal Mode
0
ON
Free Run Mode: Never wait for any trigger.
1
LOWRES
Resolution
4
1
read-write
BITS_10
10-bit resolution. For higher resolution by averaging, refer to Section 8.15 "ADC Extended Mode Register"
0
BITS_8
8-bit resolution
1
PRESCAL
Prescaler Rate Selection
8
8
read-write
SLEEP
Sleep Mode
5
1
read-write
NORMAL
Normal Mode: The ADC core and reference voltage circuitry are kept ON between conversions
0
SLEEP
Sleep Mode: The ADC core and reference voltage circuitry are OFF between conversions
1
STARTUP
Start Up Time
16
4
read-write
SUT0
0 periods of ADC Clock
0x0
SUT8
8 periods of ADC Clock
0x1
SUT16
16 periods of ADC Clock
0x2
SUT24
24 periods of ADC Clock
0x3
SUT64
64 periods of ADC Clock
0x4
SUT80
80 periods of ADC Clock
0x5
SUT96
96 periods of ADC Clock
0x6
SUT112
112 periods of ADC Clock
0x7
SUT512
512 periods of ADC Clock
0x8
SUT576
576 periods of ADC Clock
0x9
SUT640
640 periods of ADC Clock
0xA
SUT704
704 periods of ADC Clock
0xB
SUT768
768 periods of ADC Clock
0xC
SUT832
832 periods of ADC Clock
0xD
SUT896
896 periods of ADC Clock
0xE
SUT960
960 periods of ADC Clock
0xF
TRACKTIM
Tracking Time
24
4
read-write
TRGEN
Trigger Enable
0
1
read-write
DIS
Hardware triggers are disabled. Starting a conversion is only possible by software.
0
EN
Hardware trigger selected by TRGSEL field is enabled.
1
TRGSEL
Trigger Selection
1
3
read-write
ADC_TRIG0
-
0x0
ADC_TRIG1
Timer Counter Channel 0 Output
0x1
ADC_TRIG2
Timer Counter Channel 1 Output
0x2
ADC_TRIG3
Timer Counter Channel 2 Output
0x3
ADC_TRIG4
Timer Counter Channel 3 Output
0x4
ADC_TRIG5
Timer Counter Channel 4 Output
0x5
ADC_TRIG6
Timer Counter Channel 5 Output
0x6
USEQ
User Sequence Enable
31
1
read-write
NUM_ORDER
Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index.
0
REG_ORDER
User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and can be used to convert the same channel several times.
1
OVER
Overrun Status Register
0x3C
32
read-only
n
0x0
0x0
OVRE0
Overrun Error 0
0
1
read-only
OVRE1
Overrun Error 1
1
1
read-only
OVRE2
Overrun Error 2
2
1
read-only
OVRE3
Overrun Error 3
3
1
read-only
OVRE6
Overrun Error 6
6
1
read-only
OVRE7
Overrun Error 7
7
1
read-only
PTCR
Transfer Control Register
0x120
32
write-only
n
0x0
0x0
RXTDIS
Receiver Transfer Disable
1
1
write-only
RXTEN
Receiver Transfer Enable
0
1
write-only
TXTDIS
Transmitter Transfer Disable
9
1
write-only
TXTEN
Transmitter Transfer Enable
8
1
write-only
PTSR
Transfer Status Register
0x124
32
read-only
n
0x0
0x0
RXTEN
Receiver Transfer Enable
0
1
read-only
TXTEN
Transmitter Transfer Enable
8
1
read-only
RCR
Receive Counter Register
0x104
32
read-write
n
0x0
0x0
RXCTR
Receive Counter Register
0
16
read-write
RNCR
Receive Next Counter Register
0x114
32
read-write
n
0x0
0x0
RXNCTR
Receive Next Counter
0
16
read-write
RNPR
Receive Next Pointer Register
0x110
32
read-write
n
0x0
0x0
RXNPTR
Receive Next Pointer
0
32
read-write
RPR
Receive Pointer Register
0x100
32
read-write
n
0x0
0x0
RXPTR
Receive Pointer Register
0
32
read-write
SEQR1
Channel Sequence 1 Register
0x8
32
read-write
n
0x0
0x0
USCH1
User Sequence Number 1
0
4
read-write
USCH2
User Sequence Number 2
4
4
read-write
USCH3
User Sequence Number 3
8
4
read-write
USCH4
User Sequence Number 4
12
4
read-write
USCH5
User Sequence Number 5
16
4
read-write
USCH6
User Sequence Number 6
20
4
read-write
TEMPCWR
Temperature Compare Window Register
0x38
32
read-write
n
0x0
0x0
THIGHTHRES
Temperature High Threshold
16
12
read-write
TLOWTHRES
Temperature Low Threshold
0
12
read-write
TEMPMR
Temperature Sensor Mode Register
0x34
32
read-write
n
0x0
0x0
TEMPCMPMOD
Temperature Comparison Mode
4
2
read-write
LOW
Generates an event when the converted data is lower than the low threshold of the window.
0x0
HIGH
Generates an event when the converted data is higher than the high threshold of the window.
0x1
IN
Generates an event when the converted data is in the comparison window.
0x2
OUT
Generates an event when the converted data is out of the comparison window.
0x3
TEMPON
Temperature Sensor ON
0
1
read-write
WPMR
Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protect Enable
0
1
read-write
WPKEY
Write Protect Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0
0x414443
WPSR
Write Protection Status Register
0xE8
32
read-only
n
0x0
0x0
WPVS
Write Protection Violation Status
0
1
read-only
WPVSRC
Write Protection Violation Source
8
16
read-only
AES
Advanced Encryption Standard
AES
0x0
0x0
0x50
registers
n
AES
36
AADLENR
Additional Authenticated Data Length Register
0x70
32
read-write
n
0x0
0x0
AADLEN
Additional Authenticated Data Length
0
32
read-write
CLENR
Plaintext/Ciphertext Length Register
0x74
32
read-write
n
0x0
0x0
CLEN
Plaintext/Ciphertext Length
0
32
read-write
CR
Control Register
0x0
32
write-only
n
0x0
0x0
START
Start Processing
0
1
write-only
SWRST
Software Reset
8
1
write-only
CTRR
GCM Encryption Counter Value Register
0x98
32
read-only
n
0x0
0x0
CTR
GCM Encryption Counter
0
32
read-only
GCMHR0
GCM H Word Register
0x9C
32
read-write
n
H
GCM H Word x
0
32
read-write
GCMHR1
GCM H Word Register
0xA0
32
read-write
n
H
GCM H Word x
0
32
read-write
GCMHR2
GCM H Word Register
0xA4
32
read-write
n
H
GCM H Word x
0
32
read-write
GCMHR3
GCM H Word Register
0xA8
32
read-write
n
H
GCM H Word x
0
32
read-write
GCMHR[0]
GCM H Word Register
0x138
32
read-write
n
0x0
0x0
H
GCM H Word x
0
32
read-write
GCMHR[1]
GCM H Word Register
0x1D8
32
read-write
n
0x0
0x0
H
GCM H Word x
0
32
read-write
GCMHR[2]
GCM H Word Register
0x27C
32
read-write
n
0x0
0x0
H
GCM H Word x
0
32
read-write
GCMHR[3]
GCM H Word Register
0x324
32
read-write
n
0x0
0x0
H
GCM H Word x
0
32
read-write
GHASHR0
GCM Intermediate Hash Word Register
0x78
32
read-write
n
GHASH
Intermediate GCM Hash Word x
0
32
read-write
GHASHR1
GCM Intermediate Hash Word Register
0x7C
32
read-write
n
GHASH
Intermediate GCM Hash Word x
0
32
read-write
GHASHR2
GCM Intermediate Hash Word Register
0x80
32
read-write
n
GHASH
Intermediate GCM Hash Word x
0
32
read-write
GHASHR3
GCM Intermediate Hash Word Register
0x84
32
read-write
n
GHASH
Intermediate GCM Hash Word x
0
32
read-write
GHASHR[0]
GCM Intermediate Hash Word Register
0xF0
32
read-write
n
0x0
0x0
GHASH
Intermediate GCM Hash Word x
0
32
read-write
GHASHR[1]
GCM Intermediate Hash Word Register
0x16C
32
read-write
n
0x0
0x0
GHASH
Intermediate GCM Hash Word x
0
32
read-write
GHASHR[2]
GCM Intermediate Hash Word Register
0x1EC
32
read-write
n
0x0
0x0
GHASH
Intermediate GCM Hash Word x
0
32
read-write
GHASHR[3]
GCM Intermediate Hash Word Register
0x270
32
read-write
n
0x0
0x0
GHASH
Intermediate GCM Hash Word x
0
32
read-write
IDATAR0
Input Data Register
0x40
32
write-only
n
IDATA
Input Data Word
0
32
write-only
IDATAR1
Input Data Register
0x44
32
write-only
n
IDATA
Input Data Word
0
32
write-only
IDATAR2
Input Data Register
0x48
32
write-only
n
IDATA
Input Data Word
0
32
write-only
IDATAR3
Input Data Register
0x4C
32
write-only
n
IDATA
Input Data Word
0
32
write-only
IDATAR[0]
Input Data Register
0x80
32
write-only
n
0x0
0x0
IDATA
Input Data Word
0
32
write-only
IDATAR[1]
Input Data Register
0xC4
32
write-only
n
0x0
0x0
IDATA
Input Data Word
0
32
write-only
IDATAR[2]
Input Data Register
0x10C
32
write-only
n
0x0
0x0
IDATA
Input Data Word
0
32
write-only
IDATAR[3]
Input Data Register
0x158
32
write-only
n
0x0
0x0
IDATA
Input Data Word
0
32
write-only
IDR
Interrupt Disable Register
0x14
32
write-only
n
0x0
0x0
DATRDY
Data Ready Interrupt Disable
0
1
write-only
ENDRX
End of Receive Buffer Interrupt Disable
1
1
write-only
ENDTX
End of Transmit Buffer Interrupt Disable
2
1
write-only
RXBUFF
Receive Buffer Full Interrupt Disable
3
1
write-only
TAGRDY
GCM Tag Ready Interrupt Disable
16
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Disable
4
1
write-only
URAD
Unspecified Register Access Detection Interrupt Disable
8
1
write-only
IER
Interrupt Enable Register
0x10
32
write-only
n
0x0
0x0
DATRDY
Data Ready Interrupt Enable
0
1
write-only
ENDRX
End of Receive Buffer Interrupt Enable
1
1
write-only
ENDTX
End of Transmit Buffer Interrupt Enable
2
1
write-only
RXBUFF
Receive Buffer Full Interrupt Enable
3
1
write-only
TAGRDY
GCM Tag Ready Interrupt Enable
16
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Enable
4
1
write-only
URAD
Unspecified Register Access Detection Interrupt Enable
8
1
write-only
IMR
Interrupt Mask Register
0x18
32
read-only
n
0x0
0x0
DATRDY
Data Ready Interrupt Mask
0
1
read-only
ENDRX
End of Receive Buffer Interrupt Mask
1
1
read-only
ENDTX
End of Transmit Buffer Interrupt Mask
2
1
read-only
RXBUFF
Receive Buffer Full Interrupt Mask
3
1
read-only
TAGRDY
GCM Tag Ready Interrupt Mask
16
1
read-only
TXBUFE
Transmit Buffer Empty Interrupt Mask
4
1
read-only
URAD
Unspecified Register Access Detection Interrupt Mask
8
1
read-only
ISR
Interrupt Status Register
0x1C
32
read-only
n
0x0
0x0
DATRDY
Data Ready
0
1
read-only
ENDRX
End of RX Buffer
1
1
read-only
ENDTX
End of TX Buffer
2
1
read-only
RXBUFF
RX Buffer Full
3
1
read-only
TAGRDY
GCM Tag Ready
16
1
read-only
TXBUFE
TX Buffer Empty
4
1
read-only
URAD
Unspecified Register Access Detection Status
8
1
read-only
URAT
Unspecified Register Access
12
4
read-only
IDR_WR_PROCESSING
Input Data Register written during the data processing when SMOD = 0x2 mode.
0x0
ODR_RD_PROCESSING
Output Data Register read during the data processing.
0x1
MR_WR_PROCESSING
Mode Register written during the data processing.
0x2
ODR_RD_SUBKGEN
Output Data Register read during the sub-keys generation.
0x3
MR_WR_SUBKGEN
Mode Register written during the sub-keys generation.
0x4
WOR_RD_ACCESS
Write-only register read access.
0x5
IVR0
Initialization Vector Register
0x60
32
write-only
n
IV
Initialization Vector
0
32
write-only
IVR1
Initialization Vector Register
0x64
32
write-only
n
IV
Initialization Vector
0
32
write-only
IVR2
Initialization Vector Register
0x68
32
write-only
n
IV
Initialization Vector
0
32
write-only
IVR3
Initialization Vector Register
0x6C
32
write-only
n
IV
Initialization Vector
0
32
write-only
IVR[0]
Initialization Vector Register
0xC0
32
write-only
n
0x0
0x0
IV
Initialization Vector
0
32
write-only
IVR[1]
Initialization Vector Register
0x124
32
write-only
n
0x0
0x0
IV
Initialization Vector
0
32
write-only
IVR[2]
Initialization Vector Register
0x18C
32
write-only
n
0x0
0x0
IV
Initialization Vector
0
32
write-only
IVR[3]
Initialization Vector Register
0x1F8
32
write-only
n
0x0
0x0
IV
Initialization Vector
0
32
write-only
KEYWR0
Key Word Register
0x20
32
write-only
n
KEYW
Key Word
0
32
write-only
KEYWR1
Key Word Register
0x24
32
write-only
n
KEYW
Key Word
0
32
write-only
KEYWR2
Key Word Register
0x28
32
write-only
n
KEYW
Key Word
0
32
write-only
KEYWR3
Key Word Register
0x2C
32
write-only
n
KEYW
Key Word
0
32
write-only
KEYWR4
Key Word Register
0x30
32
write-only
n
KEYW
Key Word
0
32
write-only
KEYWR5
Key Word Register
0x34
32
write-only
n
KEYW
Key Word
0
32
write-only
KEYWR6
Key Word Register
0x38
32
write-only
n
KEYW
Key Word
0
32
write-only
KEYWR7
Key Word Register
0x3C
32
write-only
n
KEYW
Key Word
0
32
write-only
KEYWR[0]
Key Word Register
0x40
32
write-only
n
0x0
0x0
KEYW
Key Word
0
32
write-only
KEYWR[1]
Key Word Register
0x64
32
write-only
n
0x0
0x0
KEYW
Key Word
0
32
write-only
KEYWR[2]
Key Word Register
0x8C
32
write-only
n
0x0
0x0
KEYW
Key Word
0
32
write-only
KEYWR[3]
Key Word Register
0xB8
32
write-only
n
0x0
0x0
KEYW
Key Word
0
32
write-only
KEYWR[4]
Key Word Register
0xE8
32
write-only
n
0x0
0x0
KEYW
Key Word
0
32
write-only
KEYWR[5]
Key Word Register
0x11C
32
write-only
n
0x0
0x0
KEYW
Key Word
0
32
write-only
KEYWR[6]
Key Word Register
0x154
32
write-only
n
0x0
0x0
KEYW
Key Word
0
32
write-only
KEYWR[7]
Key Word Register
0x190
32
write-only
n
0x0
0x0
KEYW
Key Word
0
32
write-only
MR
Mode Register
0x4
32
read-write
n
0x0
0x0
CFBS
Cipher Feedback Data Size
16
3
read-write
SIZE_128BIT
128-bit
0x0
SIZE_64BIT
64-bit
0x1
SIZE_32BIT
32-bit
0x2
SIZE_16BIT
16-bit
0x3
SIZE_8BIT
8-bit
0x4
CIPHER
Processing Mode
0
1
read-write
CKEY
Key
20
4
read-write
PASSWD
This field must be written with 0xE the first time that AES_MR is programmed. For subsequent programming of the AES_MR, any value can be written, including that of 0xE.Always reads as 0.
0xE
DUALBUFF
Dual Input Buffer
3
1
read-write
INACTIVE
AES_IDATARx cannot be written during processing of previous block.
0x0
ACTIVE
AES_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files.
0x1
GTAGEN
GCM Automatic Tag Generation Enable
1
1
read-write
KEYSIZE
Key Size
10
2
read-write
AES128
AES Key Size is 128 bits
0x0
AES192
AES Key Size is 192 bits
0x1
AES256
AES Key Size is 256 bits
0x2
LOD
Last Output Data Mode
15
1
read-write
OPMOD
Operation Mode
12
3
read-write
ECB
ECB: Electronic Code Book mode
0x0
CBC
CBC: Cipher Block Chaining mode
0x1
OFB
OFB: Output Feedback mode
0x2
CFB
CFB: Cipher Feedback mode
0x3
CTR
CTR: Counter mode (16-bit internal counter)
0x4
GCM
GCM: Galois/Counter mode
0x5
PROCDLY
Processing Delay
4
4
read-write
SMOD
Start Mode
8
2
read-write
MANUAL_START
Manual Mode
0x0
AUTO_START
Auto Mode
0x1
IDATAR0_START
AES_IDATAR0 access only Auto Mode
0x2
ODATAR0
Output Data Register
0x50
32
read-only
n
ODATA
Output Data
0
32
read-only
ODATAR1
Output Data Register
0x54
32
read-only
n
ODATA
Output Data
0
32
read-only
ODATAR2
Output Data Register
0x58
32
read-only
n
ODATA
Output Data
0
32
read-only
ODATAR3
Output Data Register
0x5C
32
read-only
n
ODATA
Output Data
0
32
read-only
ODATAR[0]
Output Data Register
0xA0
32
read-only
n
0x0
0x0
ODATA
Output Data
0
32
read-only
ODATAR[1]
Output Data Register
0xF4
32
read-only
n
0x0
0x0
ODATA
Output Data
0
32
read-only
ODATAR[2]
Output Data Register
0x14C
32
read-only
n
0x0
0x0
ODATA
Output Data
0
32
read-only
ODATAR[3]
Output Data Register
0x1A8
32
read-only
n
0x0
0x0
ODATA
Output Data
0
32
read-only
PTCR
Transfer Control Register
0x120
32
write-only
n
0x0
0x0
RXTDIS
Receiver Transfer Disable
1
1
write-only
RXTEN
Receiver Transfer Enable
0
1
write-only
TXTDIS
Transmitter Transfer Disable
9
1
write-only
TXTEN
Transmitter Transfer Enable
8
1
write-only
PTSR
Transfer Status Register
0x124
32
read-only
n
0x0
0x0
RXTEN
Receiver Transfer Enable
0
1
read-only
TXTEN
Transmitter Transfer Enable
8
1
read-only
RCR
Receive Counter Register
0x104
32
read-write
n
0x0
0x0
RXCTR
Receive Counter Register
0
16
read-write
RNCR
Receive Next Counter Register
0x114
32
read-write
n
0x0
0x0
RXNCTR
Receive Next Counter
0
16
read-write
RNPR
Receive Next Pointer Register
0x110
32
read-write
n
0x0
0x0
RXNPTR
Receive Next Pointer
0
32
read-write
RPR
Receive Pointer Register
0x100
32
read-write
n
0x0
0x0
RXPTR
Receive Pointer Register
0
32
read-write
TAGR0
GCM Authentication Tag Word Register
0x88
32
read-only
n
TAG
GCM Authentication Tag x
0
32
read-only
TAGR1
GCM Authentication Tag Word Register
0x8C
32
read-only
n
TAG
GCM Authentication Tag x
0
32
read-only
TAGR2
GCM Authentication Tag Word Register
0x90
32
read-only
n
TAG
GCM Authentication Tag x
0
32
read-only
TAGR3
GCM Authentication Tag Word Register
0x94
32
read-only
n
TAG
GCM Authentication Tag x
0
32
read-only
TAGR[0]
GCM Authentication Tag Word Register
0x110
32
read-only
n
0x0
0x0
TAG
GCM Authentication Tag x
0
32
read-only
TAGR[1]
GCM Authentication Tag Word Register
0x19C
32
read-only
n
0x0
0x0
TAG
GCM Authentication Tag x
0
32
read-only
TAGR[2]
GCM Authentication Tag Word Register
0x22C
32
read-only
n
0x0
0x0
TAG
GCM Authentication Tag x
0
32
read-only
TAGR[3]
GCM Authentication Tag Word Register
0x2C0
32
read-only
n
0x0
0x0
TAG
GCM Authentication Tag x
0
32
read-only
TCR
Transmit Counter Register
0x10C
32
read-write
n
0x0
0x0
TXCTR
Transmit Counter Register
0
16
read-write
TNCR
Transmit Next Counter Register
0x11C
32
read-write
n
0x0
0x0
TXNCTR
Transmit Counter Next
0
16
read-write
TNPR
Transmit Next Pointer Register
0x118
32
read-write
n
0x0
0x0
TXNPTR
Transmit Next Pointer
0
32
read-write
TPR
Transmit Pointer Register
0x108
32
read-write
n
0x0
0x0
TXPTR
Transmit Counter Register
0
32
read-write
CHIPID
Chip Identifier
CHIPID
0x0
0x0
0xC0
registers
n
CIDR
Chip ID Register
0x0
32
read-only
n
0x0
0x0
ARCH
Architecture Identifier
20
8
read-only
SAM4CxxC
SAM4CxC (100-pin version)
0x64
EPROC
Embedded Processor
5
3
read-only
ARM946ES
ARM946ES
0x1
ARM7TDMI
ARM7TDMI
0x2
CM3
Cortex-M3
0x3
ARM920T
ARM920T
0x4
ARM926EJS
ARM926EJS
0x5
CA5
Cortex-A5
0x6
CM4
Cortex-M4
0x7
EXT
Extension Flag
31
1
read-only
NVPSIZ
Nonvolatile Program Memory Size
8
4
read-only
NONE
None
0x0
8K
8 Kbytes
0x1
16K
16 Kbytes
0x2
32K
32 Kbytes
0x3
64K
64 Kbytes
0x5
128K
128 Kbytes
0x7
160K
160 Kbytes
0x8
256K
256 Kbytes
0x9
512K
512 Kbytes
0xA
1024K
1024 Kbytes
0xC
2048K
2048 Kbytes
0xE
NVPSIZ2
Second Nonvolatile Program Memory Size
12
4
read-only
NONE
None
0x0
8K
8 Kbytes
0x1
16K
16 Kbytes
0x2
32K
32 Kbytes
0x3
64K
64 Kbytes
0x5
128K
128 Kbytes
0x7
256K
256 Kbytes
0x9
512K
512 Kbytes
0xA
1024K
1024 Kbytes
0xC
2048K
2048 Kbytes
0xE
NVPTYP
Nonvolatile Program Memory Type
28
3
read-only
ROM
ROM
0x0
ROMLESS
ROMless or on-chip Flash
0x1
FLASH
Embedded Flash Memory
0x2
ROM_FLASH
ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size
0x3
SRAM
SRAM emulating ROM
0x4
SRAMSIZ
Internal SRAM Size
16
4
read-only
48K
48 Kbytes
0x0
192K
192 Kbytes
0x1
384K
384 Kbytes
0x2
6K
6 Kbytes
0x3
24K
24 Kbytes
0x4
4K
4 Kbytes
0x5
80K
80 Kbytes
0x6
160K
160 Kbytes
0x7
8K
8 Kbytes
0x8
16K
16 Kbytes
0x9
32K
32 Kbytes
0xA
64K
64 Kbytes
0xB
128K
128 Kbytes
0xC
256K
256 Kbytes
0xD
96K
96 Kbytes
0xE
512K
512 Kbytes
0xF
VERSION
Version of the Device
0
5
read-only
EXID
Chip ID Extension Register
0x4
32
read-only
n
0x0
0x0
EXID
Chip ID Extension
0
32
read-only
SAM4CMP
SAM4C + 3-phase EMAFE
0x1
SAM4CMS
SAM4C + 2-phase EMAFE
0x2
CMCC0
Cortex-M Cache Controller 0
CMCC
0x0
0x0
0x50
registers
n
CTRL
Cache Controller Control Register
0x8
32
write-only
n
0x0
0x0
CEN
Cache Controller Enable
0
1
write-only
MAINT0
Cache Controller Maintenance Register 0
0x20
32
write-only
n
0x0
0x0
INVALL
Cache Controller Invalidate All
0
1
write-only
MAINT1
Cache Controller Maintenance Register 1
0x24
32
write-only
n
0x0
0x0
INDEX
Invalidate Index
4
5
write-only
WAY
Invalidate Way
30
2
write-only
WAY0
Way 0 is selection for index invalidation
0x0
WAY1
Way 1 is selection for index invalidation
0x1
WAY2
Way 2 is selection for index invalidation
0x2
WAY3
Way 3 is selection for index invalidation
0x3
MCFG
Cache Controller Monitor Configuration Register
0x28
32
read-write
n
0x0
0x0
MODE
Cache Controller Monitor Counter Mode
0
2
read-write
CYCLE_COUNT
Cycle counter
0x0
IHIT_COUNT
Instruction hit counter
0x1
DHIT_COUNT
Data hit counter
0x2
MCTRL
Cache Controller Monitor Control Register
0x30
32
write-only
n
0x0
0x0
SWRST
Monitor
0
1
write-only
MEN
Cache Controller Monitor Enable Register
0x2C
32
read-write
n
0x0
0x0
MENABLE
Cache Controller Monitor Enable
0
1
read-write
MSR
Cache Controller Monitor Status Register
0x34
32
read-only
n
0x0
0x0
EVENT_CNT
Monitor Event Counter
0
32
read-only
SR
Cache Controller Status Register
0xC
32
read-only
n
0x0
0x0
CSTS
Cache Controller Status
0
1
read-only
TYPE
Cache Controller Type Register
0x0
32
read-only
n
0x0
0x0
CLSIZE
Cache LIne Size
11
3
read-only
CLSIZE_1KB
Cache Line Size 4 Bytes
0x0
CLSIZE_2KB
Cache Line Size 8 Bytes
0x1
CLSIZE_4KB
Cache Line Size 16 Bytes
0x2
CLSIZE_8KB
Cache Line Size 32 Bytes
0x3
CSIZE
Data Cache Size
8
3
read-only
CSIZE_1KB
Data Cache Size 1 Kbyte
0x0
CSIZE_2KB
Data Cache Size 2 Kbytes
0x1
CSIZE_4KB
Data Cache Size 4 Kbytes
0x2
CSIZE_8KB
Data Cache Size 8 Kbytes
0x3
LCKDOWN
Lock Down Supported
7
1
read-only
LRUP
Least Recently Used Policy Supported
3
1
read-only
RANDP
Random Selection Policy Supported
2
1
read-only
RRP
Random Selection Policy Supported
4
1
read-only
WAYNUM
Number of Ways
5
2
read-only
DMAPPED
Direct Mapped Cache
0x0
ARCH2WAY
2-WAY set associative
0x1
ARCH4WAY
4-WAY set associative
0x2
ARCH8WAY
8-WAY set associative
0x3
CMCC1
Cortex-M Cache Controller 1
CMCC
0x0
0x0
0x50
registers
n
CTRL
Cache Controller Control Register
0x8
32
write-only
n
0x0
0x0
CEN
Cache Controller Enable
0
1
write-only
MAINT0
Cache Controller Maintenance Register 0
0x20
32
write-only
n
0x0
0x0
INVALL
Cache Controller Invalidate All
0
1
write-only
MAINT1
Cache Controller Maintenance Register 1
0x24
32
write-only
n
0x0
0x0
INDEX
Invalidate Index
4
5
write-only
WAY
Invalidate Way
30
2
write-only
WAY0
Way 0 is selection for index invalidation
0x0
WAY1
Way 1 is selection for index invalidation
0x1
WAY2
Way 2 is selection for index invalidation
0x2
WAY3
Way 3 is selection for index invalidation
0x3
MCFG
Cache Controller Monitor Configuration Register
0x28
32
read-write
n
0x0
0x0
MODE
Cache Controller Monitor Counter Mode
0
2
read-write
CYCLE_COUNT
Cycle counter
0x0
IHIT_COUNT
Instruction hit counter
0x1
DHIT_COUNT
Data hit counter
0x2
MCTRL
Cache Controller Monitor Control Register
0x30
32
write-only
n
0x0
0x0
SWRST
Monitor
0
1
write-only
MEN
Cache Controller Monitor Enable Register
0x2C
32
read-write
n
0x0
0x0
MENABLE
Cache Controller Monitor Enable
0
1
read-write
MSR
Cache Controller Monitor Status Register
0x34
32
read-only
n
0x0
0x0
EVENT_CNT
Monitor Event Counter
0
32
read-only
SR
Cache Controller Status Register
0xC
32
read-only
n
0x0
0x0
CSTS
Cache Controller Status
0
1
read-only
TYPE
Cache Controller Type Register
0x0
32
read-only
n
0x0
0x0
CLSIZE
Cache LIne Size
11
3
read-only
CLSIZE_1KB
Cache Line Size 4 Bytes
0x0
CLSIZE_2KB
Cache Line Size 8 Bytes
0x1
CLSIZE_4KB
Cache Line Size 16 Bytes
0x2
CLSIZE_8KB
Cache Line Size 32 Bytes
0x3
CSIZE
Data Cache Size
8
3
read-only
CSIZE_1KB
Data Cache Size 1 Kbyte
0x0
CSIZE_2KB
Data Cache Size 2 Kbytes
0x1
CSIZE_4KB
Data Cache Size 4 Kbytes
0x2
CSIZE_8KB
Data Cache Size 8 Kbytes
0x3
LCKDOWN
Lock Down Supported
7
1
read-only
LRUP
Least Recently Used Policy Supported
3
1
read-only
RANDP
Random Selection Policy Supported
2
1
read-only
RRP
Random Selection Policy Supported
4
1
read-only
WAYNUM
Number of Ways
5
2
read-only
DMAPPED
Direct Mapped Cache
0x0
ARCH2WAY
2-WAY set associative
0x1
ARCH4WAY
4-WAY set associative
0x2
ARCH8WAY
8-WAY set associative
0x3
EFC0
Embedded Flash Controller 0
EFC
0x0
0x0
0x200
registers
n
EFC0
6
FCR
EEFC Flash Command Register
0x4
32
write-only
n
0x0
0x0
FARG
Flash Command Argument
8
16
write-only
FCMD
Flash Command
0
8
write-only
GETD
Get Flash descriptor
0x00
WP
Write page
0x01
WPL
Write page and lock
0x02
EWP
Erase page and write page
0x03
EWPL
Erase page and write page then lock
0x04
EA
Erase all
0x05
EPL
Erase plane
0x06
EPA
Erase pages
0x07
SLB
Set lock bit
0x08
CLB
Clear lock bit
0x09
GLB
Get lock bit
0x0A
SGPB
Set GPNVM bit
0x0B
CGPB
Clear GPNVM bit
0x0C
GGPB
Get GPNVM bit
0x0D
STUI
Start read unique identifier
0x0E
SPUI
Stop read unique identifier
0x0F
GCALB
Get CALIB bit
0x10
ES
Erase sector
0x11
WUS
Write user signature
0x12
EUS
Erase user signature
0x13
STUS
Start read user signature
0x14
SPUS
Stop read user signature
0x15
FKEY
Flash Writing Protection Key
24
8
write-only
PASSWD
The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started.
0x5A
FMR
EEFC Flash Mode Register
0x0
32
read-write
n
0x0
0x0
CLOE
Code Loop Optimization Enable
26
1
read-write
FAM
Flash Access Mode
24
1
read-write
FRDY
Flash Ready Interrupt Enable
0
1
read-write
FWS
Flash Wait State
8
4
read-write
SCOD
Sequential Code Optimization Disable
16
1
read-write
FRR
EEFC Flash Result Register
0xC
32
read-only
n
0x0
0x0
FVALUE
Flash Result Value
0
32
read-only
FSR
EEFC Flash Status Register
0x8
32
read-only
n
0x0
0x0
FCMDE
Flash Command Error Status
1
1
read-only
FLERR
Flash Error Status
3
1
read-only
FLOCKE
Flash Lock Error Status
2
1
read-only
FRDY
Flash Ready Status
0
1
read-only
MECCELSB
Multiple ECC Error on LSB Part of the Memory Flash Data Bus
17
1
read-only
MECCEMSB
Multiple ECC Error on MSB Part of the Memory Flash Data Bus
19
1
read-only
UECCELSB
Unique ECC Error on LSB Part of the Memory Flash Data Bus
16
1
read-only
UECCEMSB
Unique ECC Error on MSB Part of the Memory Flash Data Bus
18
1
read-only
GPBR
General Purpose Backup Registers
SYSC
0x0
0x0
0x200
registers
n
GPBR0
General Purpose Backup Register
0x0
32
read-write
n
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR1
General Purpose Backup Register
0x4
32
read-write
n
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR10
General Purpose Backup Register
0x28
32
read-write
n
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR11
General Purpose Backup Register
0x2C
32
read-write
n
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR12
General Purpose Backup Register
0x30
32
read-write
n
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR13
General Purpose Backup Register
0x34
32
read-write
n
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR14
General Purpose Backup Register
0x38
32
read-write
n
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR15
General Purpose Backup Register
0x3C
32
read-write
n
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR2
General Purpose Backup Register
0x8
32
read-write
n
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR3
General Purpose Backup Register
0xC
32
read-write
n
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR4
General Purpose Backup Register
0x10
32
read-write
n
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR5
General Purpose Backup Register
0x14
32
read-write
n
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR6
General Purpose Backup Register
0x18
32
read-write
n
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR7
General Purpose Backup Register
0x1C
32
read-write
n
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR8
General Purpose Backup Register
0x20
32
read-write
n
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR9
General Purpose Backup Register
0x24
32
read-write
n
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR[0]
General Purpose Backup Register
0x0
32
read-write
n
0x0
0x0
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR[10]
General Purpose Backup Register
0xDC
32
read-write
n
0x0
0x0
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR[11]
General Purpose Backup Register
0x108
32
read-write
n
0x0
0x0
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR[12]
General Purpose Backup Register
0x138
32
read-write
n
0x0
0x0
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR[13]
General Purpose Backup Register
0x16C
32
read-write
n
0x0
0x0
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR[14]
General Purpose Backup Register
0x1A4
32
read-write
n
0x0
0x0
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR[15]
General Purpose Backup Register
0x1E0
32
read-write
n
0x0
0x0
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR[1]
General Purpose Backup Register
0x4
32
read-write
n
0x0
0x0
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR[2]
General Purpose Backup Register
0xC
32
read-write
n
0x0
0x0
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR[3]
General Purpose Backup Register
0x18
32
read-write
n
0x0
0x0
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR[4]
General Purpose Backup Register
0x28
32
read-write
n
0x0
0x0
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR[5]
General Purpose Backup Register
0x3C
32
read-write
n
0x0
0x0
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR[6]
General Purpose Backup Register
0x54
32
read-write
n
0x0
0x0
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR[7]
General Purpose Backup Register
0x70
32
read-write
n
0x0
0x0
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR[8]
General Purpose Backup Register
0x90
32
read-write
n
0x0
0x0
GPBR_VALUE
Value of GPBR x
0
32
read-write
GPBR[9]
General Purpose Backup Register
0xB4
32
read-write
n
0x0
0x0
GPBR_VALUE
Value of GPBR x
0
32
read-write
ICM
Integrity Check Monitor
ICM
0x0
0x0
0x50
registers
n
ICM
34
CFG
Configuration Register
0x0
32
read-write
n
0x0
0x0
ASCD
Automatic Switch To Compare Digest
8
1
read-write
BBC
Bus Burden Control
4
4
read-write
DAPROT
Region Descriptor Area Protection
24
6
read-write
DUALBUFF
Dual Input Buffer
9
1
read-write
EOMDIS
End of Monitoring Disable
1
1
read-write
HAPROT
Region Hash Area Protection
16
6
read-write
SLBDIS
Secondary List Branching Disable
2
1
read-write
UALGO
User SHA Algorithm
13
3
read-write
SHA1
SHA1 algorithm processed
0x0
SHA256
SHA256 algorithm processed
0x1
SHA224
SHA224 algorithm processed
0x4
UIHASH
User Initial Hash Value
12
1
read-write
WBDIS
Write Back Disable
0
1
read-write
CTRL
Control Register
0x4
32
write-only
n
0x0
0x0
DISABLE
ICM Disable Register
1
1
write-only
ENABLE
ICM Enable
0
1
write-only
REHASH
Recompute Internal Hash
4
4
write-only
RMDIS
Region Monitoring Disable
8
4
write-only
RMEN
Region Monitoring Enable
12
4
write-only
SWRST
Software Reset
2
1
write-only
DSCR
Region Descriptor Area Start Address Register
0x30
32
read-write
n
0x0
0x0
DASA
Descriptor Area Start Address
6
26
read-write
HASH
Region Hash Area Start Address Register
0x34
32
read-write
n
0x0
0x0
HASA
Hash Area Start Address
7
25
read-write
IDR
Interrupt Disable Register
0x14
32
write-only
n
0x0
0x0
RBE
Region Bus Error Interrupt Disable
8
4
write-only
RDM
Region Digest Mismatch Interrupt Disable
4
4
write-only
REC
Region End bit Condition detected Interrupt Disable
16
4
write-only
RHC
Region Hash Completed Interrupt Disable
0
4
write-only
RSU
Region Status Updated Interrupt Disable
20
4
write-only
RWC
Region Wrap Condition Detected Interrupt Disable
12
4
write-only
URAD
Undefined Register Access Detection Interrupt Disable
24
1
write-only
IER
Interrupt Enable Register
0x10
32
write-only
n
0x0
0x0
RBE
Region Bus Error Interrupt Enable
8
4
write-only
RDM
Region Digest Mismatch Interrupt Enable
4
4
write-only
REC
Region End bit Condition Detected Interrupt Enable
16
4
write-only
RHC
Region Hash Completed Interrupt Enable
0
4
write-only
RSU
Region Status Updated Interrupt Disable
20
4
write-only
RWC
Region Wrap Condition detected Interrupt Enable
12
4
write-only
URAD
Undefined Register Access Detection Interrupt Enable
24
1
write-only
IMR
Interrupt Mask Register
0x18
32
read-only
n
0x0
0x0
RBE
Region Bus Error Interrupt Mask
8
4
read-only
RDM
Region Digest Mismatch Interrupt Mask
4
4
read-only
REC
Region End bit Condition Detected Interrupt Mask
16
4
read-only
RHC
Region Hash Completed Interrupt Mask
0
4
read-only
RSU
Region Status Updated Interrupt Mask
20
4
read-only
RWC
Region Wrap Condition Detected Interrupt Mask
12
4
read-only
URAD
Undefined Register Access Detection Interrupt Mask
24
1
read-only
ISR
Interrupt Status Register
0x1C
32
read-only
n
0x0
0x0
RBE
Region Bus Error
8
4
read-only
RDM
Region Digest Mismatch
4
4
read-only
REC
Region End bit Condition Detected
16
4
read-only
RHC
Region Hash Completed
0
4
read-only
RSU
Region Status Updated Detected
20
4
read-only
RWC
Region Wrap Condition Detected
12
4
read-only
URAD
Undefined Register Access Detection Status
24
1
read-only
SR
Status Register
0x8
32
write-only
n
0x0
0x0
ENABLE
ICM Controller Enable Register
0
1
write-only
RAWRMDIS
RAW Region Monitoring Disabled Status
8
4
write-only
RMDIS
Region Monitoring Disabled Status
12
4
write-only
UASR
Undefined Access Status Register
0x20
32
read-only
n
0x0
0x0
URAT
Undefined Register Access Trace
0
3
read-only
UNSPEC_STRUCT_MEMBER
Unspecified structure member set to one detected when the descriptor is loaded.
0x0
ICM_CFG_MODIFIED
ICM_CFG modified during active monitoring.
0x1
ICM_DSCR_MODIFIED
ICM_DSCR modified during active monitoring.
0x2
ICM_HASH_MODIFIED
ICM_HASH modified during active monitoring
0x3
READ_ACCESS
Write-only register read access
0x4
UIHVAL0
User Initial Hash Value 0 Register
0x38
32
write-only
n
VAL
Initial Hash Value
0
32
write-only
UIHVAL1
User Initial Hash Value 0 Register
0x3C
32
write-only
n
VAL
Initial Hash Value
0
32
write-only
UIHVAL2
User Initial Hash Value 0 Register
0x40
32
write-only
n
VAL
Initial Hash Value
0
32
write-only
UIHVAL3
User Initial Hash Value 0 Register
0x44
32
write-only
n
VAL
Initial Hash Value
0
32
write-only
UIHVAL4
User Initial Hash Value 0 Register
0x48
32
write-only
n
VAL
Initial Hash Value
0
32
write-only
UIHVAL5
User Initial Hash Value 0 Register
0x4C
32
write-only
n
VAL
Initial Hash Value
0
32
write-only
UIHVAL6
User Initial Hash Value 0 Register
0x50
32
write-only
n
VAL
Initial Hash Value
0
32
write-only
UIHVAL7
User Initial Hash Value 0 Register
0x54
32
write-only
n
VAL
Initial Hash Value
0
32
write-only
UIHVAL[0]
User Initial Hash Value 0 Register
0x70
32
write-only
n
0x0
0x0
VAL
Initial Hash Value
0
32
write-only
UIHVAL[1]
User Initial Hash Value 0 Register
0xAC
32
write-only
n
0x0
0x0
VAL
Initial Hash Value
0
32
write-only
UIHVAL[2]
User Initial Hash Value 0 Register
0xEC
32
write-only
n
0x0
0x0
VAL
Initial Hash Value
0
32
write-only
UIHVAL[3]
User Initial Hash Value 0 Register
0x130
32
write-only
n
0x0
0x0
VAL
Initial Hash Value
0
32
write-only
UIHVAL[4]
User Initial Hash Value 0 Register
0x178
32
write-only
n
0x0
0x0
VAL
Initial Hash Value
0
32
write-only
UIHVAL[5]
User Initial Hash Value 0 Register
0x1C4
32
write-only
n
0x0
0x0
VAL
Initial Hash Value
0
32
write-only
UIHVAL[6]
User Initial Hash Value 0 Register
0x214
32
write-only
n
0x0
0x0
VAL
Initial Hash Value
0
32
write-only
UIHVAL[7]
User Initial Hash Value 0 Register
0x268
32
write-only
n
0x0
0x0
VAL
Initial Hash Value
0
32
write-only
IPC0
Interprocessor Communication 0
IPC
0x0
0x0
0x50
registers
n
IPC0
31
ICCR
Interrupt Clear Command Register
0x4
32
write-only
n
0x0
0x0
IRQ0
Interrupt Clear
0
1
write-only
IRQ1
Interrupt Clear
1
1
write-only
IRQ10
Interrupt Clear
10
1
write-only
IRQ11
Interrupt Clear
11
1
write-only
IRQ12
Interrupt Clear
12
1
write-only
IRQ13
Interrupt Clear
13
1
write-only
IRQ14
Interrupt Clear
14
1
write-only
IRQ15
Interrupt Clear
15
1
write-only
IRQ16
Interrupt Clear
16
1
write-only
IRQ17
Interrupt Clear
17
1
write-only
IRQ18
Interrupt Clear
18
1
write-only
IRQ19
Interrupt Clear
19
1
write-only
IRQ2
Interrupt Clear
2
1
write-only
IRQ20
Interrupt Clear
20
1
write-only
IRQ21
Interrupt Clear
21
1
write-only
IRQ22
Interrupt Clear
22
1
write-only
IRQ23
Interrupt Clear
23
1
write-only
IRQ24
Interrupt Clear
24
1
write-only
IRQ25
Interrupt Clear
25
1
write-only
IRQ26
Interrupt Clear
26
1
write-only
IRQ27
Interrupt Clear
27
1
write-only
IRQ28
Interrupt Clear
28
1
write-only
IRQ29
Interrupt Clear
29
1
write-only
IRQ3
Interrupt Clear
3
1
write-only
IRQ30
Interrupt Clear
30
1
write-only
IRQ31
Interrupt Clear
31
1
write-only
IRQ4
Interrupt Clear
4
1
write-only
IRQ5
Interrupt Clear
5
1
write-only
IRQ6
Interrupt Clear
6
1
write-only
IRQ7
Interrupt Clear
7
1
write-only
IRQ8
Interrupt Clear
8
1
write-only
IRQ9
Interrupt Clear
9
1
write-only
IDCR
Interrupt Disable Command Register
0x10
32
write-only
n
0x0
0x0
IRQ0
Interrupt Disable
0
1
write-only
IRQ1
Interrupt Disable
1
1
write-only
IRQ10
Interrupt Disable
10
1
write-only
IRQ11
Interrupt Disable
11
1
write-only
IRQ12
Interrupt Disable
12
1
write-only
IRQ13
Interrupt Disable
13
1
write-only
IRQ14
Interrupt Disable
14
1
write-only
IRQ15
Interrupt Disable
15
1
write-only
IRQ16
Interrupt Disable
16
1
write-only
IRQ17
Interrupt Disable
17
1
write-only
IRQ18
Interrupt Disable
18
1
write-only
IRQ19
Interrupt Disable
19
1
write-only
IRQ2
Interrupt Disable
2
1
write-only
IRQ20
Interrupt Disable
20
1
write-only
IRQ21
Interrupt Disable
21
1
write-only
IRQ22
Interrupt Disable
22
1
write-only
IRQ23
Interrupt Disable
23
1
write-only
IRQ24
Interrupt Disable
24
1
write-only
IRQ25
Interrupt Disable
25
1
write-only
IRQ26
Interrupt Disable
26
1
write-only
IRQ27
Interrupt Disable
27
1
write-only
IRQ28
Interrupt Disable
28
1
write-only
IRQ29
Interrupt Disable
29
1
write-only
IRQ3
Interrupt Disable
3
1
write-only
IRQ30
Interrupt Disable
30
1
write-only
IRQ31
Interrupt Disable
31
1
write-only
IRQ4
Interrupt Disable
4
1
write-only
IRQ5
Interrupt Disable
5
1
write-only
IRQ6
Interrupt Disable
6
1
write-only
IRQ7
Interrupt Disable
7
1
write-only
IRQ8
Interrupt Disable
8
1
write-only
IRQ9
Interrupt Disable
9
1
write-only
IECR
Interrupt Enable Command Register
0xC
32
write-only
n
0x0
0x0
IRQ0
Interrupt Enable
0
1
write-only
IRQ1
Interrupt Enable
1
1
write-only
IRQ10
Interrupt Enable
10
1
write-only
IRQ11
Interrupt Enable
11
1
write-only
IRQ12
Interrupt Enable
12
1
write-only
IRQ13
Interrupt Enable
13
1
write-only
IRQ14
Interrupt Enable
14
1
write-only
IRQ15
Interrupt Enable
15
1
write-only
IRQ16
Interrupt Enable
16
1
write-only
IRQ17
Interrupt Enable
17
1
write-only
IRQ18
Interrupt Enable
18
1
write-only
IRQ19
Interrupt Enable
19
1
write-only
IRQ2
Interrupt Enable
2
1
write-only
IRQ20
Interrupt Enable
20
1
write-only
IRQ21
Interrupt Enable
21
1
write-only
IRQ22
Interrupt Enable
22
1
write-only
IRQ23
Interrupt Enable
23
1
write-only
IRQ24
Interrupt Enable
24
1
write-only
IRQ25
Interrupt Enable
25
1
write-only
IRQ26
Interrupt Enable
26
1
write-only
IRQ27
Interrupt Enable
27
1
write-only
IRQ28
Interrupt Enable
28
1
write-only
IRQ29
Interrupt Enable
29
1
write-only
IRQ3
Interrupt Enable
3
1
write-only
IRQ30
Interrupt Enable
30
1
write-only
IRQ31
Interrupt Enable
31
1
write-only
IRQ4
Interrupt Enable
4
1
write-only
IRQ5
Interrupt Enable
5
1
write-only
IRQ6
Interrupt Enable
6
1
write-only
IRQ7
Interrupt Enable
7
1
write-only
IRQ8
Interrupt Enable
8
1
write-only
IRQ9
Interrupt Enable
9
1
write-only
IMR
Interrupt Mask Register
0x14
32
read-only
n
0x0
0x0
IRQ0
Interrupt Mask
0
1
read-only
IRQ1
Interrupt Mask
1
1
read-only
IRQ10
Interrupt Mask
10
1
read-only
IRQ11
Interrupt Mask
11
1
read-only
IRQ12
Interrupt Mask
12
1
read-only
IRQ13
Interrupt Mask
13
1
read-only
IRQ14
Interrupt Mask
14
1
read-only
IRQ15
Interrupt Mask
15
1
read-only
IRQ16
Interrupt Mask
16
1
read-only
IRQ17
Interrupt Mask
17
1
read-only
IRQ18
Interrupt Mask
18
1
read-only
IRQ19
Interrupt Mask
19
1
read-only
IRQ2
Interrupt Mask
2
1
read-only
IRQ20
Interrupt Mask
20
1
read-only
IRQ21
Interrupt Mask
21
1
read-only
IRQ22
Interrupt Mask
22
1
read-only
IRQ23
Interrupt Mask
23
1
read-only
IRQ24
Interrupt Mask
24
1
read-only
IRQ25
Interrupt Mask
25
1
read-only
IRQ26
Interrupt Mask
26
1
read-only
IRQ27
Interrupt Mask
27
1
read-only
IRQ28
Interrupt Mask
28
1
read-only
IRQ29
Interrupt Mask
29
1
read-only
IRQ3
Interrupt Mask
3
1
read-only
IRQ30
Interrupt Mask
30
1
read-only
IRQ31
Interrupt Mask
31
1
read-only
IRQ4
Interrupt Mask
4
1
read-only
IRQ5
Interrupt Mask
5
1
read-only
IRQ6
Interrupt Mask
6
1
read-only
IRQ7
Interrupt Mask
7
1
read-only
IRQ8
Interrupt Mask
8
1
read-only
IRQ9
Interrupt Mask
9
1
read-only
IPR
Interrupt Pending Register
0x8
32
read-only
n
0x0
0x0
IRQ0
Interrupt Pending
0
1
read-only
IRQ1
Interrupt Pending
1
1
read-only
IRQ10
Interrupt Pending
10
1
read-only
IRQ11
Interrupt Pending
11
1
read-only
IRQ12
Interrupt Pending
12
1
read-only
IRQ13
Interrupt Pending
13
1
read-only
IRQ14
Interrupt Pending
14
1
read-only
IRQ15
Interrupt Pending
15
1
read-only
IRQ16
Interrupt Pending
16
1
read-only
IRQ17
Interrupt Pending
17
1
read-only
IRQ18
Interrupt Pending
18
1
read-only
IRQ19
Interrupt Pending
19
1
read-only
IRQ2
Interrupt Pending
2
1
read-only
IRQ20
Interrupt Pending
20
1
read-only
IRQ21
Interrupt Pending
21
1
read-only
IRQ22
Interrupt Pending
22
1
read-only
IRQ23
Interrupt Pending
23
1
read-only
IRQ24
Interrupt Pending
24
1
read-only
IRQ25
Interrupt Pending
25
1
read-only
IRQ26
Interrupt Pending
26
1
read-only
IRQ27
Interrupt Pending
27
1
read-only
IRQ28
Interrupt Pending
28
1
read-only
IRQ29
Interrupt Pending
29
1
read-only
IRQ3
Interrupt Pending
3
1
read-only
IRQ30
Interrupt Pending
30
1
read-only
IRQ31
Interrupt Pending
31
1
read-only
IRQ4
Interrupt Pending
4
1
read-only
IRQ5
Interrupt Pending
5
1
read-only
IRQ6
Interrupt Pending
6
1
read-only
IRQ7
Interrupt Pending
7
1
read-only
IRQ8
Interrupt Pending
8
1
read-only
IRQ9
Interrupt Pending
9
1
read-only
ISCR
Interrupt Set Command Register
0x0
32
write-only
n
0x0
0x0
IRQ0
Interrupt Set
0
1
write-only
IRQ1
Interrupt Set
1
1
write-only
IRQ10
Interrupt Set
10
1
write-only
IRQ11
Interrupt Set
11
1
write-only
IRQ12
Interrupt Set
12
1
write-only
IRQ13
Interrupt Set
13
1
write-only
IRQ14
Interrupt Set
14
1
write-only
IRQ15
Interrupt Set
15
1
write-only
IRQ16
Interrupt Set
16
1
write-only
IRQ17
Interrupt Set
17
1
write-only
IRQ18
Interrupt Set
18
1
write-only
IRQ19
Interrupt Set
19
1
write-only
IRQ2
Interrupt Set
2
1
write-only
IRQ20
Interrupt Set
20
1
write-only
IRQ21
Interrupt Set
21
1
write-only
IRQ22
Interrupt Set
22
1
write-only
IRQ23
Interrupt Set
23
1
write-only
IRQ24
Interrupt Set
24
1
write-only
IRQ25
Interrupt Set
25
1
write-only
IRQ26
Interrupt Set
26
1
write-only
IRQ27
Interrupt Set
27
1
write-only
IRQ28
Interrupt Set
28
1
write-only
IRQ29
Interrupt Set
29
1
write-only
IRQ3
Interrupt Set
3
1
write-only
IRQ30
Interrupt Set
30
1
write-only
IRQ31
Interrupt Set
31
1
write-only
IRQ4
Interrupt Set
4
1
write-only
IRQ5
Interrupt Set
5
1
write-only
IRQ6
Interrupt Set
6
1
write-only
IRQ7
Interrupt Set
7
1
write-only
IRQ8
Interrupt Set
8
1
write-only
IRQ9
Interrupt Set
9
1
write-only
ISR
Interrupt Status Register
0x18
32
read-only
n
0x0
0x0
IRQ0
Current Interrupt Identifier
0
1
read-only
IRQ1
Current Interrupt Identifier
1
1
read-only
IRQ10
Current Interrupt Identifier
10
1
read-only
IRQ11
Current Interrupt Identifier
11
1
read-only
IRQ12
Current Interrupt Identifier
12
1
read-only
IRQ13
Current Interrupt Identifier
13
1
read-only
IRQ14
Current Interrupt Identifier
14
1
read-only
IRQ15
Current Interrupt Identifier
15
1
read-only
IRQ16
Current Interrupt Identifier
16
1
read-only
IRQ17
Current Interrupt Identifier
17
1
read-only
IRQ18
Current Interrupt Identifier
18
1
read-only
IRQ19
Current Interrupt Identifier
19
1
read-only
IRQ2
Current Interrupt Identifier
2
1
read-only
IRQ20
Current Interrupt Identifier
20
1
read-only
IRQ21
Current Interrupt Identifier
21
1
read-only
IRQ22
Current Interrupt Identifier
22
1
read-only
IRQ23
Current Interrupt Identifier
23
1
read-only
IRQ24
Current Interrupt Identifier
24
1
read-only
IRQ25
Current Interrupt Identifier
25
1
read-only
IRQ26
Current Interrupt Identifier
26
1
read-only
IRQ27
Current Interrupt Identifier
27
1
read-only
IRQ28
Current Interrupt Identifier
28
1
read-only
IRQ29
Current Interrupt Identifier
29
1
read-only
IRQ3
Current Interrupt Identifier
3
1
read-only
IRQ30
Current Interrupt Identifier
30
1
read-only
IRQ31
Current Interrupt Identifier
31
1
read-only
IRQ4
Current Interrupt Identifier
4
1
read-only
IRQ5
Current Interrupt Identifier
5
1
read-only
IRQ6
Current Interrupt Identifier
6
1
read-only
IRQ7
Current Interrupt Identifier
7
1
read-only
IRQ8
Current Interrupt Identifier
8
1
read-only
IRQ9
Current Interrupt Identifier
9
1
read-only
IPC1
Interprocessor Communication 1
IPC
0x0
0x0
0x50
registers
n
IPC1
39
ICCR
Interrupt Clear Command Register
0x4
32
write-only
n
0x0
0x0
IRQ0
Interrupt Clear
0
1
write-only
IRQ1
Interrupt Clear
1
1
write-only
IRQ10
Interrupt Clear
10
1
write-only
IRQ11
Interrupt Clear
11
1
write-only
IRQ12
Interrupt Clear
12
1
write-only
IRQ13
Interrupt Clear
13
1
write-only
IRQ14
Interrupt Clear
14
1
write-only
IRQ15
Interrupt Clear
15
1
write-only
IRQ16
Interrupt Clear
16
1
write-only
IRQ17
Interrupt Clear
17
1
write-only
IRQ18
Interrupt Clear
18
1
write-only
IRQ19
Interrupt Clear
19
1
write-only
IRQ2
Interrupt Clear
2
1
write-only
IRQ20
Interrupt Clear
20
1
write-only
IRQ21
Interrupt Clear
21
1
write-only
IRQ22
Interrupt Clear
22
1
write-only
IRQ23
Interrupt Clear
23
1
write-only
IRQ24
Interrupt Clear
24
1
write-only
IRQ25
Interrupt Clear
25
1
write-only
IRQ26
Interrupt Clear
26
1
write-only
IRQ27
Interrupt Clear
27
1
write-only
IRQ28
Interrupt Clear
28
1
write-only
IRQ29
Interrupt Clear
29
1
write-only
IRQ3
Interrupt Clear
3
1
write-only
IRQ30
Interrupt Clear
30
1
write-only
IRQ31
Interrupt Clear
31
1
write-only
IRQ4
Interrupt Clear
4
1
write-only
IRQ5
Interrupt Clear
5
1
write-only
IRQ6
Interrupt Clear
6
1
write-only
IRQ7
Interrupt Clear
7
1
write-only
IRQ8
Interrupt Clear
8
1
write-only
IRQ9
Interrupt Clear
9
1
write-only
IDCR
Interrupt Disable Command Register
0x10
32
write-only
n
0x0
0x0
IRQ0
Interrupt Disable
0
1
write-only
IRQ1
Interrupt Disable
1
1
write-only
IRQ10
Interrupt Disable
10
1
write-only
IRQ11
Interrupt Disable
11
1
write-only
IRQ12
Interrupt Disable
12
1
write-only
IRQ13
Interrupt Disable
13
1
write-only
IRQ14
Interrupt Disable
14
1
write-only
IRQ15
Interrupt Disable
15
1
write-only
IRQ16
Interrupt Disable
16
1
write-only
IRQ17
Interrupt Disable
17
1
write-only
IRQ18
Interrupt Disable
18
1
write-only
IRQ19
Interrupt Disable
19
1
write-only
IRQ2
Interrupt Disable
2
1
write-only
IRQ20
Interrupt Disable
20
1
write-only
IRQ21
Interrupt Disable
21
1
write-only
IRQ22
Interrupt Disable
22
1
write-only
IRQ23
Interrupt Disable
23
1
write-only
IRQ24
Interrupt Disable
24
1
write-only
IRQ25
Interrupt Disable
25
1
write-only
IRQ26
Interrupt Disable
26
1
write-only
IRQ27
Interrupt Disable
27
1
write-only
IRQ28
Interrupt Disable
28
1
write-only
IRQ29
Interrupt Disable
29
1
write-only
IRQ3
Interrupt Disable
3
1
write-only
IRQ30
Interrupt Disable
30
1
write-only
IRQ31
Interrupt Disable
31
1
write-only
IRQ4
Interrupt Disable
4
1
write-only
IRQ5
Interrupt Disable
5
1
write-only
IRQ6
Interrupt Disable
6
1
write-only
IRQ7
Interrupt Disable
7
1
write-only
IRQ8
Interrupt Disable
8
1
write-only
IRQ9
Interrupt Disable
9
1
write-only
IECR
Interrupt Enable Command Register
0xC
32
write-only
n
0x0
0x0
IRQ0
Interrupt Enable
0
1
write-only
IRQ1
Interrupt Enable
1
1
write-only
IRQ10
Interrupt Enable
10
1
write-only
IRQ11
Interrupt Enable
11
1
write-only
IRQ12
Interrupt Enable
12
1
write-only
IRQ13
Interrupt Enable
13
1
write-only
IRQ14
Interrupt Enable
14
1
write-only
IRQ15
Interrupt Enable
15
1
write-only
IRQ16
Interrupt Enable
16
1
write-only
IRQ17
Interrupt Enable
17
1
write-only
IRQ18
Interrupt Enable
18
1
write-only
IRQ19
Interrupt Enable
19
1
write-only
IRQ2
Interrupt Enable
2
1
write-only
IRQ20
Interrupt Enable
20
1
write-only
IRQ21
Interrupt Enable
21
1
write-only
IRQ22
Interrupt Enable
22
1
write-only
IRQ23
Interrupt Enable
23
1
write-only
IRQ24
Interrupt Enable
24
1
write-only
IRQ25
Interrupt Enable
25
1
write-only
IRQ26
Interrupt Enable
26
1
write-only
IRQ27
Interrupt Enable
27
1
write-only
IRQ28
Interrupt Enable
28
1
write-only
IRQ29
Interrupt Enable
29
1
write-only
IRQ3
Interrupt Enable
3
1
write-only
IRQ30
Interrupt Enable
30
1
write-only
IRQ31
Interrupt Enable
31
1
write-only
IRQ4
Interrupt Enable
4
1
write-only
IRQ5
Interrupt Enable
5
1
write-only
IRQ6
Interrupt Enable
6
1
write-only
IRQ7
Interrupt Enable
7
1
write-only
IRQ8
Interrupt Enable
8
1
write-only
IRQ9
Interrupt Enable
9
1
write-only
IMR
Interrupt Mask Register
0x14
32
read-only
n
0x0
0x0
IRQ0
Interrupt Mask
0
1
read-only
IRQ1
Interrupt Mask
1
1
read-only
IRQ10
Interrupt Mask
10
1
read-only
IRQ11
Interrupt Mask
11
1
read-only
IRQ12
Interrupt Mask
12
1
read-only
IRQ13
Interrupt Mask
13
1
read-only
IRQ14
Interrupt Mask
14
1
read-only
IRQ15
Interrupt Mask
15
1
read-only
IRQ16
Interrupt Mask
16
1
read-only
IRQ17
Interrupt Mask
17
1
read-only
IRQ18
Interrupt Mask
18
1
read-only
IRQ19
Interrupt Mask
19
1
read-only
IRQ2
Interrupt Mask
2
1
read-only
IRQ20
Interrupt Mask
20
1
read-only
IRQ21
Interrupt Mask
21
1
read-only
IRQ22
Interrupt Mask
22
1
read-only
IRQ23
Interrupt Mask
23
1
read-only
IRQ24
Interrupt Mask
24
1
read-only
IRQ25
Interrupt Mask
25
1
read-only
IRQ26
Interrupt Mask
26
1
read-only
IRQ27
Interrupt Mask
27
1
read-only
IRQ28
Interrupt Mask
28
1
read-only
IRQ29
Interrupt Mask
29
1
read-only
IRQ3
Interrupt Mask
3
1
read-only
IRQ30
Interrupt Mask
30
1
read-only
IRQ31
Interrupt Mask
31
1
read-only
IRQ4
Interrupt Mask
4
1
read-only
IRQ5
Interrupt Mask
5
1
read-only
IRQ6
Interrupt Mask
6
1
read-only
IRQ7
Interrupt Mask
7
1
read-only
IRQ8
Interrupt Mask
8
1
read-only
IRQ9
Interrupt Mask
9
1
read-only
IPR
Interrupt Pending Register
0x8
32
read-only
n
0x0
0x0
IRQ0
Interrupt Pending
0
1
read-only
IRQ1
Interrupt Pending
1
1
read-only
IRQ10
Interrupt Pending
10
1
read-only
IRQ11
Interrupt Pending
11
1
read-only
IRQ12
Interrupt Pending
12
1
read-only
IRQ13
Interrupt Pending
13
1
read-only
IRQ14
Interrupt Pending
14
1
read-only
IRQ15
Interrupt Pending
15
1
read-only
IRQ16
Interrupt Pending
16
1
read-only
IRQ17
Interrupt Pending
17
1
read-only
IRQ18
Interrupt Pending
18
1
read-only
IRQ19
Interrupt Pending
19
1
read-only
IRQ2
Interrupt Pending
2
1
read-only
IRQ20
Interrupt Pending
20
1
read-only
IRQ21
Interrupt Pending
21
1
read-only
IRQ22
Interrupt Pending
22
1
read-only
IRQ23
Interrupt Pending
23
1
read-only
IRQ24
Interrupt Pending
24
1
read-only
IRQ25
Interrupt Pending
25
1
read-only
IRQ26
Interrupt Pending
26
1
read-only
IRQ27
Interrupt Pending
27
1
read-only
IRQ28
Interrupt Pending
28
1
read-only
IRQ29
Interrupt Pending
29
1
read-only
IRQ3
Interrupt Pending
3
1
read-only
IRQ30
Interrupt Pending
30
1
read-only
IRQ31
Interrupt Pending
31
1
read-only
IRQ4
Interrupt Pending
4
1
read-only
IRQ5
Interrupt Pending
5
1
read-only
IRQ6
Interrupt Pending
6
1
read-only
IRQ7
Interrupt Pending
7
1
read-only
IRQ8
Interrupt Pending
8
1
read-only
IRQ9
Interrupt Pending
9
1
read-only
ISCR
Interrupt Set Command Register
0x0
32
write-only
n
0x0
0x0
IRQ0
Interrupt Set
0
1
write-only
IRQ1
Interrupt Set
1
1
write-only
IRQ10
Interrupt Set
10
1
write-only
IRQ11
Interrupt Set
11
1
write-only
IRQ12
Interrupt Set
12
1
write-only
IRQ13
Interrupt Set
13
1
write-only
IRQ14
Interrupt Set
14
1
write-only
IRQ15
Interrupt Set
15
1
write-only
IRQ16
Interrupt Set
16
1
write-only
IRQ17
Interrupt Set
17
1
write-only
IRQ18
Interrupt Set
18
1
write-only
IRQ19
Interrupt Set
19
1
write-only
IRQ2
Interrupt Set
2
1
write-only
IRQ20
Interrupt Set
20
1
write-only
IRQ21
Interrupt Set
21
1
write-only
IRQ22
Interrupt Set
22
1
write-only
IRQ23
Interrupt Set
23
1
write-only
IRQ24
Interrupt Set
24
1
write-only
IRQ25
Interrupt Set
25
1
write-only
IRQ26
Interrupt Set
26
1
write-only
IRQ27
Interrupt Set
27
1
write-only
IRQ28
Interrupt Set
28
1
write-only
IRQ29
Interrupt Set
29
1
write-only
IRQ3
Interrupt Set
3
1
write-only
IRQ30
Interrupt Set
30
1
write-only
IRQ31
Interrupt Set
31
1
write-only
IRQ4
Interrupt Set
4
1
write-only
IRQ5
Interrupt Set
5
1
write-only
IRQ6
Interrupt Set
6
1
write-only
IRQ7
Interrupt Set
7
1
write-only
IRQ8
Interrupt Set
8
1
write-only
IRQ9
Interrupt Set
9
1
write-only
ISR
Interrupt Status Register
0x18
32
read-only
n
0x0
0x0
IRQ0
Current Interrupt Identifier
0
1
read-only
IRQ1
Current Interrupt Identifier
1
1
read-only
IRQ10
Current Interrupt Identifier
10
1
read-only
IRQ11
Current Interrupt Identifier
11
1
read-only
IRQ12
Current Interrupt Identifier
12
1
read-only
IRQ13
Current Interrupt Identifier
13
1
read-only
IRQ14
Current Interrupt Identifier
14
1
read-only
IRQ15
Current Interrupt Identifier
15
1
read-only
IRQ16
Current Interrupt Identifier
16
1
read-only
IRQ17
Current Interrupt Identifier
17
1
read-only
IRQ18
Current Interrupt Identifier
18
1
read-only
IRQ19
Current Interrupt Identifier
19
1
read-only
IRQ2
Current Interrupt Identifier
2
1
read-only
IRQ20
Current Interrupt Identifier
20
1
read-only
IRQ21
Current Interrupt Identifier
21
1
read-only
IRQ22
Current Interrupt Identifier
22
1
read-only
IRQ23
Current Interrupt Identifier
23
1
read-only
IRQ24
Current Interrupt Identifier
24
1
read-only
IRQ25
Current Interrupt Identifier
25
1
read-only
IRQ26
Current Interrupt Identifier
26
1
read-only
IRQ27
Current Interrupt Identifier
27
1
read-only
IRQ28
Current Interrupt Identifier
28
1
read-only
IRQ29
Current Interrupt Identifier
29
1
read-only
IRQ3
Current Interrupt Identifier
3
1
read-only
IRQ30
Current Interrupt Identifier
30
1
read-only
IRQ31
Current Interrupt Identifier
31
1
read-only
IRQ4
Current Interrupt Identifier
4
1
read-only
IRQ5
Current Interrupt Identifier
5
1
read-only
IRQ6
Current Interrupt Identifier
6
1
read-only
IRQ7
Current Interrupt Identifier
7
1
read-only
IRQ8
Current Interrupt Identifier
8
1
read-only
IRQ9
Current Interrupt Identifier
9
1
read-only
MATRIX0
AHB Bus Matrix 0
MATRIX
0x0
0x0
0x200
registers
n
CORE_DEBUG
Core Debug Configuration Register
0x128
32
read-write
n
0x0
0x0
CROSS_TRG0
2
1
read-write
CROSS_TRG1
1
1
read-write
MCFG0
Master Configuration Register
0x0
32
read-write
n
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG1
Master Configuration Register
0x4
32
read-write
n
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG2
Master Configuration Register
0x8
32
read-write
n
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG3
Master Configuration Register
0xC
32
read-write
n
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG4
Master Configuration Register
0x10
32
read-write
n
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG5
Master Configuration Register
0x14
32
read-write
n
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG6
Master Configuration Register
0x18
32
read-write
n
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG[0]
Master Configuration Register
0x0
32
read-write
n
0x0
0x0
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG[1]
Master Configuration Register
0x4
32
read-write
n
0x0
0x0
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG[2]
Master Configuration Register
0xC
32
read-write
n
0x0
0x0
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG[3]
Master Configuration Register
0x18
32
read-write
n
0x0
0x0
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG[4]
Master Configuration Register
0x28
32
read-write
n
0x0
0x0
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG[5]
Master Configuration Register
0x3C
32
read-write
n
0x0
0x0
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG[6]
Master Configuration Register
0x54
32
read-write
n
0x0
0x0
ULBT
Undefined Length Burst Type
0
3
read-write
PRAS0
Priority Register A for Slave 0
0x80
32
read-write
n
0x0
0x0
M0PR
Master 0 Priority
0
2
read-write
M1PR
Master 1 Priority
4
2
read-write
M2PR
Master 2 Priority
8
2
read-write
M3PR
Master 3 Priority
12
2
read-write
M4PR
Master 4 Priority
16
2
read-write
M5PR
Master 5 Priority
20
2
read-write
M6PR
Master 6 Priority
24
2
read-write
M7PR
Master 7 Priority
28
2
read-write
PRAS1
Priority Register A for Slave 1
0x88
32
read-write
n
0x0
0x0
M0PR
Master 0 Priority
0
2
read-write
M1PR
Master 1 Priority
4
2
read-write
M2PR
Master 2 Priority
8
2
read-write
M3PR
Master 3 Priority
12
2
read-write
M4PR
Master 4 Priority
16
2
read-write
M5PR
Master 5 Priority
20
2
read-write
M6PR
Master 6 Priority
24
2
read-write
M7PR
Master 7 Priority
28
2
read-write
PRAS2
Priority Register A for Slave 2
0x90
32
read-write
n
0x0
0x0
M0PR
Master 0 Priority
0
2
read-write
M1PR
Master 1 Priority
4
2
read-write
M2PR
Master 2 Priority
8
2
read-write
M3PR
Master 3 Priority
12
2
read-write
M4PR
Master 4 Priority
16
2
read-write
M5PR
Master 5 Priority
20
2
read-write
M6PR
Master 6 Priority
24
2
read-write
M7PR
Master 7 Priority
28
2
read-write
PRAS3
Priority Register A for Slave 3
0x98
32
read-write
n
0x0
0x0
M0PR
Master 0 Priority
0
2
read-write
M1PR
Master 1 Priority
4
2
read-write
M2PR
Master 2 Priority
8
2
read-write
M3PR
Master 3 Priority
12
2
read-write
M4PR
Master 4 Priority
16
2
read-write
M5PR
Master 5 Priority
20
2
read-write
M6PR
Master 6 Priority
24
2
read-write
M7PR
Master 7 Priority
28
2
read-write
PRAS4
Priority Register A for Slave 4
0xA0
32
read-write
n
0x0
0x0
M0PR
Master 0 Priority
0
2
read-write
M1PR
Master 1 Priority
4
2
read-write
M2PR
Master 2 Priority
8
2
read-write
M3PR
Master 3 Priority
12
2
read-write
M4PR
Master 4 Priority
16
2
read-write
M5PR
Master 5 Priority
20
2
read-write
M6PR
Master 6 Priority
24
2
read-write
M7PR
Master 7 Priority
28
2
read-write
PRAS5
Priority Register A for Slave 5
0xA8
32
read-write
n
0x0
0x0
M0PR
Master 0 Priority
0
2
read-write
M1PR
Master 1 Priority
4
2
read-write
M2PR
Master 2 Priority
8
2
read-write
M3PR
Master 3 Priority
12
2
read-write
M4PR
Master 4 Priority
16
2
read-write
M5PR
Master 5 Priority
20
2
read-write
M6PR
Master 6 Priority
24
2
read-write
M7PR
Master 7 Priority
28
2
read-write
PRAS6
Priority Register A for Slave 6
0xB0
32
read-write
n
0x0
0x0
M0PR
Master 0 Priority
0
2
read-write
M1PR
Master 1 Priority
4
2
read-write
M2PR
Master 2 Priority
8
2
read-write
M3PR
Master 3 Priority
12
2
read-write
M4PR
Master 4 Priority
16
2
read-write
M5PR
Master 5 Priority
20
2
read-write
M6PR
Master 6 Priority
24
2
read-write
M7PR
Master 7 Priority
28
2
read-write
PRAS7
Priority Register A for Slave 7
0xB8
32
read-write
n
0x0
0x0
M0PR
Master 0 Priority
0
2
read-write
M1PR
Master 1 Priority
4
2
read-write
M2PR
Master 2 Priority
8
2
read-write
M3PR
Master 3 Priority
12
2
read-write
M4PR
Master 4 Priority
16
2
read-write
M5PR
Master 5 Priority
20
2
read-write
M6PR
Master 6 Priority
24
2
read-write
M7PR
Master 7 Priority
28
2
read-write
SCFG0
Slave Configuration Register
0x40
32
read-write
n
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG1
Slave Configuration Register
0x44
32
read-write
n
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG2
Slave Configuration Register
0x48
32
read-write
n
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG3
Slave Configuration Register
0x4C
32
read-write
n
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG4
Slave Configuration Register
0x50
32
read-write
n
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG5
Slave Configuration Register
0x54
32
read-write
n
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG6
Slave Configuration Register
0x58
32
read-write
n
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG7
Slave Configuration Register
0x5C
32
read-write
n
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG[0]
Slave Configuration Register
0x80
32
read-write
n
0x0
0x0
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG[1]
Slave Configuration Register
0xC4
32
read-write
n
0x0
0x0
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG[2]
Slave Configuration Register
0x10C
32
read-write
n
0x0
0x0
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG[3]
Slave Configuration Register
0x158
32
read-write
n
0x0
0x0
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG[4]
Slave Configuration Register
0x1A8
32
read-write
n
0x0
0x0
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG[5]
Slave Configuration Register
0x1FC
32
read-write
n
0x0
0x0
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG[6]
Slave Configuration Register
0x254
32
read-write
n
0x0
0x0
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG[7]
Slave Configuration Register
0x2B0
32
read-write
n
0x0
0x0
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SMCNFCS
SMC Nand Flash Chip Select Configuration Register
0x11C
32
read-write
n
0x0
0x0
SMC_NFCS0
SMC NAND Flash Chip Select 0 Assignment
0
1
read-write
SMC_NFCS1
SMC NAND Flash Chip Select 1 Assignment
1
1
read-write
SMC_NFCS2
SMC NAND Flash Chip Select 2 Assignment
2
1
read-write
SMC_NFCS3
SMC NAND Flash Chip Select 3 Assignment
3
1
read-write
SMC_SEL
SMC Selection for EBI pins
31
1
read-write
SYSIO
System I/O Configuration Register
0x114
32
read-write
n
0x0
0x0
SYSIO0
PB0 or TDI Assignment
0
1
read-write
SYSIO1
PB1 or TDO/TRACESWO Assignment
1
1
read-write
SYSIO2
PB2 or TMS/SWDIO Assignment
2
1
read-write
SYSIO3
PB3 or TCK/SWCLK Assignment
3
1
read-write
SYSIO9
PC9 or ERASE Assignment
9
1
read-write
WPMR
Write Protection Mode Register
0x1E4
32
read-write
n
0x0
0x0
WPEN
Write Protect Enable
0
1
read-write
WPKEY
Write Protect Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
0x4D4154
WPSR
Write Protection Status Register
0x1E8
32
read-only
n
0x0
0x0
WPVS
Write Protection Violation Status
0
1
read-only
WPVSRC
Write Protection Violation Source
8
16
read-only
MATRIX1
AHB Bus Matrix 1
MATRIX
0x0
0x0
0x50
registers
n
CORE_DEBUG
Core Debug Configuration Register
0x128
32
read-write
n
0x0
0x0
CROSS_TRG0
2
1
read-write
CROSS_TRG1
1
1
read-write
MCFG0
Master Configuration Register
0x0
32
read-write
n
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG1
Master Configuration Register
0x4
32
read-write
n
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG2
Master Configuration Register
0x8
32
read-write
n
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG3
Master Configuration Register
0xC
32
read-write
n
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG4
Master Configuration Register
0x10
32
read-write
n
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG5
Master Configuration Register
0x14
32
read-write
n
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG6
Master Configuration Register
0x18
32
read-write
n
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG[0]
Master Configuration Register
0x0
32
read-write
n
0x0
0x0
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG[1]
Master Configuration Register
0x4
32
read-write
n
0x0
0x0
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG[2]
Master Configuration Register
0xC
32
read-write
n
0x0
0x0
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG[3]
Master Configuration Register
0x18
32
read-write
n
0x0
0x0
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG[4]
Master Configuration Register
0x28
32
read-write
n
0x0
0x0
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG[5]
Master Configuration Register
0x3C
32
read-write
n
0x0
0x0
ULBT
Undefined Length Burst Type
0
3
read-write
MCFG[6]
Master Configuration Register
0x54
32
read-write
n
0x0
0x0
ULBT
Undefined Length Burst Type
0
3
read-write
PRAS0
Priority Register A for Slave 0
0x80
32
read-write
n
0x0
0x0
M0PR
Master 0 Priority
0
2
read-write
M1PR
Master 1 Priority
4
2
read-write
M2PR
Master 2 Priority
8
2
read-write
M3PR
Master 3 Priority
12
2
read-write
M4PR
Master 4 Priority
16
2
read-write
M5PR
Master 5 Priority
20
2
read-write
M6PR
Master 6 Priority
24
2
read-write
M7PR
Master 7 Priority
28
2
read-write
PRAS1
Priority Register A for Slave 1
0x88
32
read-write
n
0x0
0x0
M0PR
Master 0 Priority
0
2
read-write
M1PR
Master 1 Priority
4
2
read-write
M2PR
Master 2 Priority
8
2
read-write
M3PR
Master 3 Priority
12
2
read-write
M4PR
Master 4 Priority
16
2
read-write
M5PR
Master 5 Priority
20
2
read-write
M6PR
Master 6 Priority
24
2
read-write
M7PR
Master 7 Priority
28
2
read-write
PRAS2
Priority Register A for Slave 2
0x90
32
read-write
n
0x0
0x0
M0PR
Master 0 Priority
0
2
read-write
M1PR
Master 1 Priority
4
2
read-write
M2PR
Master 2 Priority
8
2
read-write
M3PR
Master 3 Priority
12
2
read-write
M4PR
Master 4 Priority
16
2
read-write
M5PR
Master 5 Priority
20
2
read-write
M6PR
Master 6 Priority
24
2
read-write
M7PR
Master 7 Priority
28
2
read-write
PRAS3
Priority Register A for Slave 3
0x98
32
read-write
n
0x0
0x0
M0PR
Master 0 Priority
0
2
read-write
M1PR
Master 1 Priority
4
2
read-write
M2PR
Master 2 Priority
8
2
read-write
M3PR
Master 3 Priority
12
2
read-write
M4PR
Master 4 Priority
16
2
read-write
M5PR
Master 5 Priority
20
2
read-write
M6PR
Master 6 Priority
24
2
read-write
M7PR
Master 7 Priority
28
2
read-write
PRAS4
Priority Register A for Slave 4
0xA0
32
read-write
n
0x0
0x0
M0PR
Master 0 Priority
0
2
read-write
M1PR
Master 1 Priority
4
2
read-write
M2PR
Master 2 Priority
8
2
read-write
M3PR
Master 3 Priority
12
2
read-write
M4PR
Master 4 Priority
16
2
read-write
M5PR
Master 5 Priority
20
2
read-write
M6PR
Master 6 Priority
24
2
read-write
M7PR
Master 7 Priority
28
2
read-write
PRAS5
Priority Register A for Slave 5
0xA8
32
read-write
n
0x0
0x0
M0PR
Master 0 Priority
0
2
read-write
M1PR
Master 1 Priority
4
2
read-write
M2PR
Master 2 Priority
8
2
read-write
M3PR
Master 3 Priority
12
2
read-write
M4PR
Master 4 Priority
16
2
read-write
M5PR
Master 5 Priority
20
2
read-write
M6PR
Master 6 Priority
24
2
read-write
M7PR
Master 7 Priority
28
2
read-write
PRAS6
Priority Register A for Slave 6
0xB0
32
read-write
n
0x0
0x0
M0PR
Master 0 Priority
0
2
read-write
M1PR
Master 1 Priority
4
2
read-write
M2PR
Master 2 Priority
8
2
read-write
M3PR
Master 3 Priority
12
2
read-write
M4PR
Master 4 Priority
16
2
read-write
M5PR
Master 5 Priority
20
2
read-write
M6PR
Master 6 Priority
24
2
read-write
M7PR
Master 7 Priority
28
2
read-write
PRAS7
Priority Register A for Slave 7
0xB8
32
read-write
n
0x0
0x0
M0PR
Master 0 Priority
0
2
read-write
M1PR
Master 1 Priority
4
2
read-write
M2PR
Master 2 Priority
8
2
read-write
M3PR
Master 3 Priority
12
2
read-write
M4PR
Master 4 Priority
16
2
read-write
M5PR
Master 5 Priority
20
2
read-write
M6PR
Master 6 Priority
24
2
read-write
M7PR
Master 7 Priority
28
2
read-write
SCFG0
Slave Configuration Register
0x40
32
read-write
n
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG1
Slave Configuration Register
0x44
32
read-write
n
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG2
Slave Configuration Register
0x48
32
read-write
n
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG3
Slave Configuration Register
0x4C
32
read-write
n
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG4
Slave Configuration Register
0x50
32
read-write
n
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG5
Slave Configuration Register
0x54
32
read-write
n
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG6
Slave Configuration Register
0x58
32
read-write
n
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG7
Slave Configuration Register
0x5C
32
read-write
n
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG[0]
Slave Configuration Register
0x80
32
read-write
n
0x0
0x0
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG[1]
Slave Configuration Register
0xC4
32
read-write
n
0x0
0x0
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG[2]
Slave Configuration Register
0x10C
32
read-write
n
0x0
0x0
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG[3]
Slave Configuration Register
0x158
32
read-write
n
0x0
0x0
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG[4]
Slave Configuration Register
0x1A8
32
read-write
n
0x0
0x0
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG[5]
Slave Configuration Register
0x1FC
32
read-write
n
0x0
0x0
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG[6]
Slave Configuration Register
0x254
32
read-write
n
0x0
0x0
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SCFG[7]
Slave Configuration Register
0x2B0
32
read-write
n
0x0
0x0
DEFMSTR_TYPE
Default Master Type
16
2
read-write
FIXED_DEFMSTR
Fixed Default Master
18
4
read-write
SLOT_CYCLE
Maximum Bus Grant Duration for Masters
0
9
read-write
SMCNFCS
SMC Nand Flash Chip Select Configuration Register
0x11C
32
read-write
n
0x0
0x0
SMC_NFCS0
SMC NAND Flash Chip Select 0 Assignment
0
1
read-write
SMC_NFCS1
SMC NAND Flash Chip Select 1 Assignment
1
1
read-write
SMC_NFCS2
SMC NAND Flash Chip Select 2 Assignment
2
1
read-write
SMC_NFCS3
SMC NAND Flash Chip Select 3 Assignment
3
1
read-write
SMC_SEL
SMC Selection for EBI pins
31
1
read-write
SYSIO
System I/O Configuration Register
0x114
32
read-write
n
0x0
0x0
SYSIO0
PB0 or TDI Assignment
0
1
read-write
SYSIO1
PB1 or TDO/TRACESWO Assignment
1
1
read-write
SYSIO2
PB2 or TMS/SWDIO Assignment
2
1
read-write
SYSIO3
PB3 or TCK/SWCLK Assignment
3
1
read-write
SYSIO9
PC9 or ERASE Assignment
9
1
read-write
WPMR
Write Protection Mode Register
0x1E4
32
read-write
n
0x0
0x0
WPEN
Write Protect Enable
0
1
read-write
WPKEY
Write Protect Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
0x4D4154
WPSR
Write Protection Status Register
0x1E8
32
read-only
n
0x0
0x0
WPVS
Write Protection Violation Status
0
1
read-only
WPVSRC
Write Protection Violation Source
8
16
read-only
PIOA
Parallel Input/Output Controller A
PIO
0x0
0x0
0x200
registers
n
PIOA
11
ABCDSR0
Peripheral Select Register
0x70
32
read-write
n
P0
Peripheral Select
0
1
read-write
P1
Peripheral Select
1
1
read-write
P10
Peripheral Select
10
1
read-write
P11
Peripheral Select
11
1
read-write
P12
Peripheral Select
12
1
read-write
P13
Peripheral Select
13
1
read-write
P14
Peripheral Select
14
1
read-write
P15
Peripheral Select
15
1
read-write
P16
Peripheral Select
16
1
read-write
P17
Peripheral Select
17
1
read-write
P18
Peripheral Select
18
1
read-write
P19
Peripheral Select
19
1
read-write
P2
Peripheral Select
2
1
read-write
P20
Peripheral Select
20
1
read-write
P21
Peripheral Select
21
1
read-write
P22
Peripheral Select
22
1
read-write
P23
Peripheral Select
23
1
read-write
P24
Peripheral Select
24
1
read-write
P25
Peripheral Select
25
1
read-write
P26
Peripheral Select
26
1
read-write
P27
Peripheral Select
27
1
read-write
P28
Peripheral Select
28
1
read-write
P29
Peripheral Select
29
1
read-write
P3
Peripheral Select
3
1
read-write
P30
Peripheral Select
30
1
read-write
P31
Peripheral Select
31
1
read-write
P4
Peripheral Select
4
1
read-write
P5
Peripheral Select
5
1
read-write
P6
Peripheral Select
6
1
read-write
P7
Peripheral Select
7
1
read-write
P8
Peripheral Select
8
1
read-write
P9
Peripheral Select
9
1
read-write
ABCDSR1
Peripheral Select Register
0x74
32
read-write
n
P0
Peripheral Select
0
1
read-write
P1
Peripheral Select
1
1
read-write
P10
Peripheral Select
10
1
read-write
P11
Peripheral Select
11
1
read-write
P12
Peripheral Select
12
1
read-write
P13
Peripheral Select
13
1
read-write
P14
Peripheral Select
14
1
read-write
P15
Peripheral Select
15
1
read-write
P16
Peripheral Select
16
1
read-write
P17
Peripheral Select
17
1
read-write
P18
Peripheral Select
18
1
read-write
P19
Peripheral Select
19
1
read-write
P2
Peripheral Select
2
1
read-write
P20
Peripheral Select
20
1
read-write
P21
Peripheral Select
21
1
read-write
P22
Peripheral Select
22
1
read-write
P23
Peripheral Select
23
1
read-write
P24
Peripheral Select
24
1
read-write
P25
Peripheral Select
25
1
read-write
P26
Peripheral Select
26
1
read-write
P27
Peripheral Select
27
1
read-write
P28
Peripheral Select
28
1
read-write
P29
Peripheral Select
29
1
read-write
P3
Peripheral Select
3
1
read-write
P30
Peripheral Select
30
1
read-write
P31
Peripheral Select
31
1
read-write
P4
Peripheral Select
4
1
read-write
P5
Peripheral Select
5
1
read-write
P6
Peripheral Select
6
1
read-write
P7
Peripheral Select
7
1
read-write
P8
Peripheral Select
8
1
read-write
P9
Peripheral Select
9
1
read-write
ABCDSR[0]
Peripheral Select Register
0xE0
32
read-write
n
0x0
0x0
P0
Peripheral Select
0
1
read-write
P1
Peripheral Select
1
1
read-write
P10
Peripheral Select
10
1
read-write
P11
Peripheral Select
11
1
read-write
P12
Peripheral Select
12
1
read-write
P13
Peripheral Select
13
1
read-write
P14
Peripheral Select
14
1
read-write
P15
Peripheral Select
15
1
read-write
P16
Peripheral Select
16
1
read-write
P17
Peripheral Select
17
1
read-write
P18
Peripheral Select
18
1
read-write
P19
Peripheral Select
19
1
read-write
P2
Peripheral Select
2
1
read-write
P20
Peripheral Select
20
1
read-write
P21
Peripheral Select
21
1
read-write
P22
Peripheral Select
22
1
read-write
P23
Peripheral Select
23
1
read-write
P24
Peripheral Select
24
1
read-write
P25
Peripheral Select
25
1
read-write
P26
Peripheral Select
26
1
read-write
P27
Peripheral Select
27
1
read-write
P28
Peripheral Select
28
1
read-write
P29
Peripheral Select
29
1
read-write
P3
Peripheral Select
3
1
read-write
P30
Peripheral Select
30
1
read-write
P31
Peripheral Select
31
1
read-write
P4
Peripheral Select
4
1
read-write
P5
Peripheral Select
5
1
read-write
P6
Peripheral Select
6
1
read-write
P7
Peripheral Select
7
1
read-write
P8
Peripheral Select
8
1
read-write
P9
Peripheral Select
9
1
read-write
ABCDSR[1]
Peripheral Select Register
0x154
32
read-write
n
0x0
0x0
P0
Peripheral Select
0
1
read-write
P1
Peripheral Select
1
1
read-write
P10
Peripheral Select
10
1
read-write
P11
Peripheral Select
11
1
read-write
P12
Peripheral Select
12
1
read-write
P13
Peripheral Select
13
1
read-write
P14
Peripheral Select
14
1
read-write
P15
Peripheral Select
15
1
read-write
P16
Peripheral Select
16
1
read-write
P17
Peripheral Select
17
1
read-write
P18
Peripheral Select
18
1
read-write
P19
Peripheral Select
19
1
read-write
P2
Peripheral Select
2
1
read-write
P20
Peripheral Select
20
1
read-write
P21
Peripheral Select
21
1
read-write
P22
Peripheral Select
22
1
read-write
P23
Peripheral Select
23
1
read-write
P24
Peripheral Select
24
1
read-write
P25
Peripheral Select
25
1
read-write
P26
Peripheral Select
26
1
read-write
P27
Peripheral Select
27
1
read-write
P28
Peripheral Select
28
1
read-write
P29
Peripheral Select
29
1
read-write
P3
Peripheral Select
3
1
read-write
P30
Peripheral Select
30
1
read-write
P31
Peripheral Select
31
1
read-write
P4
Peripheral Select
4
1
read-write
P5
Peripheral Select
5
1
read-write
P6
Peripheral Select
6
1
read-write
P7
Peripheral Select
7
1
read-write
P8
Peripheral Select
8
1
read-write
P9
Peripheral Select
9
1
read-write
AIMDR
Additional Interrupt Modes Disable Register
0xB4
32
write-only
n
0x0
0x0
P0
Additional Interrupt Modes Disable
0
1
write-only
P1
Additional Interrupt Modes Disable
1
1
write-only
P10
Additional Interrupt Modes Disable
10
1
write-only
P11
Additional Interrupt Modes Disable
11
1
write-only
P12
Additional Interrupt Modes Disable
12
1
write-only
P13
Additional Interrupt Modes Disable
13
1
write-only
P14
Additional Interrupt Modes Disable
14
1
write-only
P15
Additional Interrupt Modes Disable
15
1
write-only
P16
Additional Interrupt Modes Disable
16
1
write-only
P17
Additional Interrupt Modes Disable
17
1
write-only
P18
Additional Interrupt Modes Disable
18
1
write-only
P19
Additional Interrupt Modes Disable
19
1
write-only
P2
Additional Interrupt Modes Disable
2
1
write-only
P20
Additional Interrupt Modes Disable
20
1
write-only
P21
Additional Interrupt Modes Disable
21
1
write-only
P22
Additional Interrupt Modes Disable
22
1
write-only
P23
Additional Interrupt Modes Disable
23
1
write-only
P24
Additional Interrupt Modes Disable
24
1
write-only
P25
Additional Interrupt Modes Disable
25
1
write-only
P26
Additional Interrupt Modes Disable
26
1
write-only
P27
Additional Interrupt Modes Disable
27
1
write-only
P28
Additional Interrupt Modes Disable
28
1
write-only
P29
Additional Interrupt Modes Disable
29
1
write-only
P3
Additional Interrupt Modes Disable
3
1
write-only
P30
Additional Interrupt Modes Disable
30
1
write-only
P31
Additional Interrupt Modes Disable
31
1
write-only
P4
Additional Interrupt Modes Disable
4
1
write-only
P5
Additional Interrupt Modes Disable
5
1
write-only
P6
Additional Interrupt Modes Disable
6
1
write-only
P7
Additional Interrupt Modes Disable
7
1
write-only
P8
Additional Interrupt Modes Disable
8
1
write-only
P9
Additional Interrupt Modes Disable
9
1
write-only
AIMER
Additional Interrupt Modes Enable Register
0xB0
32
write-only
n
0x0
0x0
P0
Additional Interrupt Modes Enable
0
1
write-only
P1
Additional Interrupt Modes Enable
1
1
write-only
P10
Additional Interrupt Modes Enable
10
1
write-only
P11
Additional Interrupt Modes Enable
11
1
write-only
P12
Additional Interrupt Modes Enable
12
1
write-only
P13
Additional Interrupt Modes Enable
13
1
write-only
P14
Additional Interrupt Modes Enable
14
1
write-only
P15
Additional Interrupt Modes Enable
15
1
write-only
P16
Additional Interrupt Modes Enable
16
1
write-only
P17
Additional Interrupt Modes Enable
17
1
write-only
P18
Additional Interrupt Modes Enable
18
1
write-only
P19
Additional Interrupt Modes Enable
19
1
write-only
P2
Additional Interrupt Modes Enable
2
1
write-only
P20
Additional Interrupt Modes Enable
20
1
write-only
P21
Additional Interrupt Modes Enable
21
1
write-only
P22
Additional Interrupt Modes Enable
22
1
write-only
P23
Additional Interrupt Modes Enable
23
1
write-only
P24
Additional Interrupt Modes Enable
24
1
write-only
P25
Additional Interrupt Modes Enable
25
1
write-only
P26
Additional Interrupt Modes Enable
26
1
write-only
P27
Additional Interrupt Modes Enable
27
1
write-only
P28
Additional Interrupt Modes Enable
28
1
write-only
P29
Additional Interrupt Modes Enable
29
1
write-only
P3
Additional Interrupt Modes Enable
3
1
write-only
P30
Additional Interrupt Modes Enable
30
1
write-only
P31
Additional Interrupt Modes Enable
31
1
write-only
P4
Additional Interrupt Modes Enable
4
1
write-only
P5
Additional Interrupt Modes Enable
5
1
write-only
P6
Additional Interrupt Modes Enable
6
1
write-only
P7
Additional Interrupt Modes Enable
7
1
write-only
P8
Additional Interrupt Modes Enable
8
1
write-only
P9
Additional Interrupt Modes Enable
9
1
write-only
AIMMR
Additional Interrupt Modes Mask Register
0xB8
32
read-only
n
0x0
0x0
P0
IO Line Index
0
1
read-only
P1
IO Line Index
1
1
read-only
P10
IO Line Index
10
1
read-only
P11
IO Line Index
11
1
read-only
P12
IO Line Index
12
1
read-only
P13
IO Line Index
13
1
read-only
P14
IO Line Index
14
1
read-only
P15
IO Line Index
15
1
read-only
P16
IO Line Index
16
1
read-only
P17
IO Line Index
17
1
read-only
P18
IO Line Index
18
1
read-only
P19
IO Line Index
19
1
read-only
P2
IO Line Index
2
1
read-only
P20
IO Line Index
20
1
read-only
P21
IO Line Index
21
1
read-only
P22
IO Line Index
22
1
read-only
P23
IO Line Index
23
1
read-only
P24
IO Line Index
24
1
read-only
P25
IO Line Index
25
1
read-only
P26
IO Line Index
26
1
read-only
P27
IO Line Index
27
1
read-only
P28
IO Line Index
28
1
read-only
P29
IO Line Index
29
1
read-only
P3
IO Line Index
3
1
read-only
P30
IO Line Index
30
1
read-only
P31
IO Line Index
31
1
read-only
P4
IO Line Index
4
1
read-only
P5
IO Line Index
5
1
read-only
P6
IO Line Index
6
1
read-only
P7
IO Line Index
7
1
read-only
P8
IO Line Index
8
1
read-only
P9
IO Line Index
9
1
read-only
CODR
Clear Output Data Register
0x34
32
write-only
n
0x0
0x0
P0
Clear Output Data
0
1
write-only
P1
Clear Output Data
1
1
write-only
P10
Clear Output Data
10
1
write-only
P11
Clear Output Data
11
1
write-only
P12
Clear Output Data
12
1
write-only
P13
Clear Output Data
13
1
write-only
P14
Clear Output Data
14
1
write-only
P15
Clear Output Data
15
1
write-only
P16
Clear Output Data
16
1
write-only
P17
Clear Output Data
17
1
write-only
P18
Clear Output Data
18
1
write-only
P19
Clear Output Data
19
1
write-only
P2
Clear Output Data
2
1
write-only
P20
Clear Output Data
20
1
write-only
P21
Clear Output Data
21
1
write-only
P22
Clear Output Data
22
1
write-only
P23
Clear Output Data
23
1
write-only
P24
Clear Output Data
24
1
write-only
P25
Clear Output Data
25
1
write-only
P26
Clear Output Data
26
1
write-only
P27
Clear Output Data
27
1
write-only
P28
Clear Output Data
28
1
write-only
P29
Clear Output Data
29
1
write-only
P3
Clear Output Data
3
1
write-only
P30
Clear Output Data
30
1
write-only
P31
Clear Output Data
31
1
write-only
P4
Clear Output Data
4
1
write-only
P5
Clear Output Data
5
1
write-only
P6
Clear Output Data
6
1
write-only
P7
Clear Output Data
7
1
write-only
P8
Clear Output Data
8
1
write-only
P9
Clear Output Data
9
1
write-only
DRIVER
I/O Drive Register
0x118
32
read-write
n
0x0
0x0
LINE0
Drive of PIO Line 0
0
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE1
Drive of PIO Line 1
1
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE10
Drive of PIO Line 10
10
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE11
Drive of PIO Line 11
11
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE12
Drive of PIO Line 12
12
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE13
Drive of PIO Line 13
13
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE14
Drive of PIO Line 14
14
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE15
Drive of PIO Line 15
15
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE16
Drive of PIO Line 16
16
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE17
Drive of PIO Line 17
17
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE18
Drive of PIO Line 18
18
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE19
Drive of PIO Line 19
19
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE2
Drive of PIO Line 2
2
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE20
Drive of PIO Line 20
20
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE21
Drive of PIO Line 21
21
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE22
Drive of PIO Line 22
22
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE23
Drive of PIO Line 23
23
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE24
Drive of PIO Line 24
24
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE25
Drive of PIO Line 25
25
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE26
Drive of PIO Line 26
26
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE27
Drive of PIO Line 27
27
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE28
Drive of PIO Line 28
28
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE29
Drive of PIO Line 29
29
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE3
Drive of PIO Line 3
3
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE30
Drive of PIO Line 30
30
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE31
Drive of PIO Line 31
31
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE4
Drive of PIO Line 4
4
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE5
Drive of PIO Line 5
5
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE6
Drive of PIO Line 6
6
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE7
Drive of PIO Line 7
7
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE8
Drive of PIO Line 8
8
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE9
Drive of PIO Line 9
9
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
ELSR
Edge/Level Status Register
0xC8
32
read-only
n
0x0
0x0
P0
Edge/Level Interrupt Source Selection
0
1
read-only
P1
Edge/Level Interrupt Source Selection
1
1
read-only
P10
Edge/Level Interrupt Source Selection
10
1
read-only
P11
Edge/Level Interrupt Source Selection
11
1
read-only
P12
Edge/Level Interrupt Source Selection
12
1
read-only
P13
Edge/Level Interrupt Source Selection
13
1
read-only
P14
Edge/Level Interrupt Source Selection
14
1
read-only
P15
Edge/Level Interrupt Source Selection
15
1
read-only
P16
Edge/Level Interrupt Source Selection
16
1
read-only
P17
Edge/Level Interrupt Source Selection
17
1
read-only
P18
Edge/Level Interrupt Source Selection
18
1
read-only
P19
Edge/Level Interrupt Source Selection
19
1
read-only
P2
Edge/Level Interrupt Source Selection
2
1
read-only
P20
Edge/Level Interrupt Source Selection
20
1
read-only
P21
Edge/Level Interrupt Source Selection
21
1
read-only
P22
Edge/Level Interrupt Source Selection
22
1
read-only
P23
Edge/Level Interrupt Source Selection
23
1
read-only
P24
Edge/Level Interrupt Source Selection
24
1
read-only
P25
Edge/Level Interrupt Source Selection
25
1
read-only
P26
Edge/Level Interrupt Source Selection
26
1
read-only
P27
Edge/Level Interrupt Source Selection
27
1
read-only
P28
Edge/Level Interrupt Source Selection
28
1
read-only
P29
Edge/Level Interrupt Source Selection
29
1
read-only
P3
Edge/Level Interrupt Source Selection
3
1
read-only
P30
Edge/Level Interrupt Source Selection
30
1
read-only
P31
Edge/Level Interrupt Source Selection
31
1
read-only
P4
Edge/Level Interrupt Source Selection
4
1
read-only
P5
Edge/Level Interrupt Source Selection
5
1
read-only
P6
Edge/Level Interrupt Source Selection
6
1
read-only
P7
Edge/Level Interrupt Source Selection
7
1
read-only
P8
Edge/Level Interrupt Source Selection
8
1
read-only
P9
Edge/Level Interrupt Source Selection
9
1
read-only
ESR
Edge Select Register
0xC0
32
write-only
n
0x0
0x0
P0
Edge Interrupt Selection
0
1
write-only
P1
Edge Interrupt Selection
1
1
write-only
P10
Edge Interrupt Selection
10
1
write-only
P11
Edge Interrupt Selection
11
1
write-only
P12
Edge Interrupt Selection
12
1
write-only
P13
Edge Interrupt Selection
13
1
write-only
P14
Edge Interrupt Selection
14
1
write-only
P15
Edge Interrupt Selection
15
1
write-only
P16
Edge Interrupt Selection
16
1
write-only
P17
Edge Interrupt Selection
17
1
write-only
P18
Edge Interrupt Selection
18
1
write-only
P19
Edge Interrupt Selection
19
1
write-only
P2
Edge Interrupt Selection
2
1
write-only
P20
Edge Interrupt Selection
20
1
write-only
P21
Edge Interrupt Selection
21
1
write-only
P22
Edge Interrupt Selection
22
1
write-only
P23
Edge Interrupt Selection
23
1
write-only
P24
Edge Interrupt Selection
24
1
write-only
P25
Edge Interrupt Selection
25
1
write-only
P26
Edge Interrupt Selection
26
1
write-only
P27
Edge Interrupt Selection
27
1
write-only
P28
Edge Interrupt Selection
28
1
write-only
P29
Edge Interrupt Selection
29
1
write-only
P3
Edge Interrupt Selection
3
1
write-only
P30
Edge Interrupt Selection
30
1
write-only
P31
Edge Interrupt Selection
31
1
write-only
P4
Edge Interrupt Selection
4
1
write-only
P5
Edge Interrupt Selection
5
1
write-only
P6
Edge Interrupt Selection
6
1
write-only
P7
Edge Interrupt Selection
7
1
write-only
P8
Edge Interrupt Selection
8
1
write-only
P9
Edge Interrupt Selection
9
1
write-only
FELLSR
Falling Edge/Low-Level Select Register
0xD0
32
write-only
n
0x0
0x0
P0
Falling Edge/Low-Level Interrupt Selection
0
1
write-only
P1
Falling Edge/Low-Level Interrupt Selection
1
1
write-only
P10
Falling Edge/Low-Level Interrupt Selection
10
1
write-only
P11
Falling Edge/Low-Level Interrupt Selection
11
1
write-only
P12
Falling Edge/Low-Level Interrupt Selection
12
1
write-only
P13
Falling Edge/Low-Level Interrupt Selection
13
1
write-only
P14
Falling Edge/Low-Level Interrupt Selection
14
1
write-only
P15
Falling Edge/Low-Level Interrupt Selection
15
1
write-only
P16
Falling Edge/Low-Level Interrupt Selection
16
1
write-only
P17
Falling Edge/Low-Level Interrupt Selection
17
1
write-only
P18
Falling Edge/Low-Level Interrupt Selection
18
1
write-only
P19
Falling Edge/Low-Level Interrupt Selection
19
1
write-only
P2
Falling Edge/Low-Level Interrupt Selection
2
1
write-only
P20
Falling Edge/Low-Level Interrupt Selection
20
1
write-only
P21
Falling Edge/Low-Level Interrupt Selection
21
1
write-only
P22
Falling Edge/Low-Level Interrupt Selection
22
1
write-only
P23
Falling Edge/Low-Level Interrupt Selection
23
1
write-only
P24
Falling Edge/Low-Level Interrupt Selection
24
1
write-only
P25
Falling Edge/Low-Level Interrupt Selection
25
1
write-only
P26
Falling Edge/Low-Level Interrupt Selection
26
1
write-only
P27
Falling Edge/Low-Level Interrupt Selection
27
1
write-only
P28
Falling Edge/Low-Level Interrupt Selection
28
1
write-only
P29
Falling Edge/Low-Level Interrupt Selection
29
1
write-only
P3
Falling Edge/Low-Level Interrupt Selection
3
1
write-only
P30
Falling Edge/Low-Level Interrupt Selection
30
1
write-only
P31
Falling Edge/Low-Level Interrupt Selection
31
1
write-only
P4
Falling Edge/Low-Level Interrupt Selection
4
1
write-only
P5
Falling Edge/Low-Level Interrupt Selection
5
1
write-only
P6
Falling Edge/Low-Level Interrupt Selection
6
1
write-only
P7
Falling Edge/Low-Level Interrupt Selection
7
1
write-only
P8
Falling Edge/Low-Level Interrupt Selection
8
1
write-only
P9
Falling Edge/Low-Level Interrupt Selection
9
1
write-only
FRLHSR
Fall/Rise - Low/High Status Register
0xD8
32
read-only
n
0x0
0x0
P0
Edge/Level Interrupt Source Selection
0
1
read-only
P1
Edge/Level Interrupt Source Selection
1
1
read-only
P10
Edge/Level Interrupt Source Selection
10
1
read-only
P11
Edge/Level Interrupt Source Selection
11
1
read-only
P12
Edge/Level Interrupt Source Selection
12
1
read-only
P13
Edge/Level Interrupt Source Selection
13
1
read-only
P14
Edge/Level Interrupt Source Selection
14
1
read-only
P15
Edge/Level Interrupt Source Selection
15
1
read-only
P16
Edge/Level Interrupt Source Selection
16
1
read-only
P17
Edge/Level Interrupt Source Selection
17
1
read-only
P18
Edge/Level Interrupt Source Selection
18
1
read-only
P19
Edge/Level Interrupt Source Selection
19
1
read-only
P2
Edge/Level Interrupt Source Selection
2
1
read-only
P20
Edge/Level Interrupt Source Selection
20
1
read-only
P21
Edge/Level Interrupt Source Selection
21
1
read-only
P22
Edge/Level Interrupt Source Selection
22
1
read-only
P23
Edge/Level Interrupt Source Selection
23
1
read-only
P24
Edge/Level Interrupt Source Selection
24
1
read-only
P25
Edge/Level Interrupt Source Selection
25
1
read-only
P26
Edge/Level Interrupt Source Selection
26
1
read-only
P27
Edge/Level Interrupt Source Selection
27
1
read-only
P28
Edge/Level Interrupt Source Selection
28
1
read-only
P29
Edge/Level Interrupt Source Selection
29
1
read-only
P3
Edge/Level Interrupt Source Selection
3
1
read-only
P30
Edge/Level Interrupt Source Selection
30
1
read-only
P31
Edge/Level Interrupt Source Selection
31
1
read-only
P4
Edge/Level Interrupt Source Selection
4
1
read-only
P5
Edge/Level Interrupt Source Selection
5
1
read-only
P6
Edge/Level Interrupt Source Selection
6
1
read-only
P7
Edge/Level Interrupt Source Selection
7
1
read-only
P8
Edge/Level Interrupt Source Selection
8
1
read-only
P9
Edge/Level Interrupt Source Selection
9
1
read-only
IDR
Interrupt Disable Register
0x44
32
write-only
n
0x0
0x0
P0
Input Change Interrupt Disable
0
1
write-only
P1
Input Change Interrupt Disable
1
1
write-only
P10
Input Change Interrupt Disable
10
1
write-only
P11
Input Change Interrupt Disable
11
1
write-only
P12
Input Change Interrupt Disable
12
1
write-only
P13
Input Change Interrupt Disable
13
1
write-only
P14
Input Change Interrupt Disable
14
1
write-only
P15
Input Change Interrupt Disable
15
1
write-only
P16
Input Change Interrupt Disable
16
1
write-only
P17
Input Change Interrupt Disable
17
1
write-only
P18
Input Change Interrupt Disable
18
1
write-only
P19
Input Change Interrupt Disable
19
1
write-only
P2
Input Change Interrupt Disable
2
1
write-only
P20
Input Change Interrupt Disable
20
1
write-only
P21
Input Change Interrupt Disable
21
1
write-only
P22
Input Change Interrupt Disable
22
1
write-only
P23
Input Change Interrupt Disable
23
1
write-only
P24
Input Change Interrupt Disable
24
1
write-only
P25
Input Change Interrupt Disable
25
1
write-only
P26
Input Change Interrupt Disable
26
1
write-only
P27
Input Change Interrupt Disable
27
1
write-only
P28
Input Change Interrupt Disable
28
1
write-only
P29
Input Change Interrupt Disable
29
1
write-only
P3
Input Change Interrupt Disable
3
1
write-only
P30
Input Change Interrupt Disable
30
1
write-only
P31
Input Change Interrupt Disable
31
1
write-only
P4
Input Change Interrupt Disable
4
1
write-only
P5
Input Change Interrupt Disable
5
1
write-only
P6
Input Change Interrupt Disable
6
1
write-only
P7
Input Change Interrupt Disable
7
1
write-only
P8
Input Change Interrupt Disable
8
1
write-only
P9
Input Change Interrupt Disable
9
1
write-only
IER
Interrupt Enable Register
0x40
32
write-only
n
0x0
0x0
P0
Input Change Interrupt Enable
0
1
write-only
P1
Input Change Interrupt Enable
1
1
write-only
P10
Input Change Interrupt Enable
10
1
write-only
P11
Input Change Interrupt Enable
11
1
write-only
P12
Input Change Interrupt Enable
12
1
write-only
P13
Input Change Interrupt Enable
13
1
write-only
P14
Input Change Interrupt Enable
14
1
write-only
P15
Input Change Interrupt Enable
15
1
write-only
P16
Input Change Interrupt Enable
16
1
write-only
P17
Input Change Interrupt Enable
17
1
write-only
P18
Input Change Interrupt Enable
18
1
write-only
P19
Input Change Interrupt Enable
19
1
write-only
P2
Input Change Interrupt Enable
2
1
write-only
P20
Input Change Interrupt Enable
20
1
write-only
P21
Input Change Interrupt Enable
21
1
write-only
P22
Input Change Interrupt Enable
22
1
write-only
P23
Input Change Interrupt Enable
23
1
write-only
P24
Input Change Interrupt Enable
24
1
write-only
P25
Input Change Interrupt Enable
25
1
write-only
P26
Input Change Interrupt Enable
26
1
write-only
P27
Input Change Interrupt Enable
27
1
write-only
P28
Input Change Interrupt Enable
28
1
write-only
P29
Input Change Interrupt Enable
29
1
write-only
P3
Input Change Interrupt Enable
3
1
write-only
P30
Input Change Interrupt Enable
30
1
write-only
P31
Input Change Interrupt Enable
31
1
write-only
P4
Input Change Interrupt Enable
4
1
write-only
P5
Input Change Interrupt Enable
5
1
write-only
P6
Input Change Interrupt Enable
6
1
write-only
P7
Input Change Interrupt Enable
7
1
write-only
P8
Input Change Interrupt Enable
8
1
write-only
P9
Input Change Interrupt Enable
9
1
write-only
IFDR
Glitch Input Filter Disable Register
0x24
32
write-only
n
0x0
0x0
P0
Input Filter Disable
0
1
write-only
P1
Input Filter Disable
1
1
write-only
P10
Input Filter Disable
10
1
write-only
P11
Input Filter Disable
11
1
write-only
P12
Input Filter Disable
12
1
write-only
P13
Input Filter Disable
13
1
write-only
P14
Input Filter Disable
14
1
write-only
P15
Input Filter Disable
15
1
write-only
P16
Input Filter Disable
16
1
write-only
P17
Input Filter Disable
17
1
write-only
P18
Input Filter Disable
18
1
write-only
P19
Input Filter Disable
19
1
write-only
P2
Input Filter Disable
2
1
write-only
P20
Input Filter Disable
20
1
write-only
P21
Input Filter Disable
21
1
write-only
P22
Input Filter Disable
22
1
write-only
P23
Input Filter Disable
23
1
write-only
P24
Input Filter Disable
24
1
write-only
P25
Input Filter Disable
25
1
write-only
P26
Input Filter Disable
26
1
write-only
P27
Input Filter Disable
27
1
write-only
P28
Input Filter Disable
28
1
write-only
P29
Input Filter Disable
29
1
write-only
P3
Input Filter Disable
3
1
write-only
P30
Input Filter Disable
30
1
write-only
P31
Input Filter Disable
31
1
write-only
P4
Input Filter Disable
4
1
write-only
P5
Input Filter Disable
5
1
write-only
P6
Input Filter Disable
6
1
write-only
P7
Input Filter Disable
7
1
write-only
P8
Input Filter Disable
8
1
write-only
P9
Input Filter Disable
9
1
write-only
IFER
Glitch Input Filter Enable Register
0x20
32
write-only
n
0x0
0x0
P0
Input Filter Enable
0
1
write-only
P1
Input Filter Enable
1
1
write-only
P10
Input Filter Enable
10
1
write-only
P11
Input Filter Enable
11
1
write-only
P12
Input Filter Enable
12
1
write-only
P13
Input Filter Enable
13
1
write-only
P14
Input Filter Enable
14
1
write-only
P15
Input Filter Enable
15
1
write-only
P16
Input Filter Enable
16
1
write-only
P17
Input Filter Enable
17
1
write-only
P18
Input Filter Enable
18
1
write-only
P19
Input Filter Enable
19
1
write-only
P2
Input Filter Enable
2
1
write-only
P20
Input Filter Enable
20
1
write-only
P21
Input Filter Enable
21
1
write-only
P22
Input Filter Enable
22
1
write-only
P23
Input Filter Enable
23
1
write-only
P24
Input Filter Enable
24
1
write-only
P25
Input Filter Enable
25
1
write-only
P26
Input Filter Enable
26
1
write-only
P27
Input Filter Enable
27
1
write-only
P28
Input Filter Enable
28
1
write-only
P29
Input Filter Enable
29
1
write-only
P3
Input Filter Enable
3
1
write-only
P30
Input Filter Enable
30
1
write-only
P31
Input Filter Enable
31
1
write-only
P4
Input Filter Enable
4
1
write-only
P5
Input Filter Enable
5
1
write-only
P6
Input Filter Enable
6
1
write-only
P7
Input Filter Enable
7
1
write-only
P8
Input Filter Enable
8
1
write-only
P9
Input Filter Enable
9
1
write-only
IFSCDR
Input Filter Slow Clock Disable Register
0x80
32
write-only
n
0x0
0x0
P0
Peripheral Clock Glitch Filtering Select
0
1
write-only
P1
Peripheral Clock Glitch Filtering Select
1
1
write-only
P10
Peripheral Clock Glitch Filtering Select
10
1
write-only
P11
Peripheral Clock Glitch Filtering Select
11
1
write-only
P12
Peripheral Clock Glitch Filtering Select
12
1
write-only
P13
Peripheral Clock Glitch Filtering Select
13
1
write-only
P14
Peripheral Clock Glitch Filtering Select
14
1
write-only
P15
Peripheral Clock Glitch Filtering Select
15
1
write-only
P16
Peripheral Clock Glitch Filtering Select
16
1
write-only
P17
Peripheral Clock Glitch Filtering Select
17
1
write-only
P18
Peripheral Clock Glitch Filtering Select
18
1
write-only
P19
Peripheral Clock Glitch Filtering Select
19
1
write-only
P2
Peripheral Clock Glitch Filtering Select
2
1
write-only
P20
Peripheral Clock Glitch Filtering Select
20
1
write-only
P21
Peripheral Clock Glitch Filtering Select
21
1
write-only
P22
Peripheral Clock Glitch Filtering Select
22
1
write-only
P23
Peripheral Clock Glitch Filtering Select
23
1
write-only
P24
Peripheral Clock Glitch Filtering Select
24
1
write-only
P25
Peripheral Clock Glitch Filtering Select
25
1
write-only
P26
Peripheral Clock Glitch Filtering Select
26
1
write-only
P27
Peripheral Clock Glitch Filtering Select
27
1
write-only
P28
Peripheral Clock Glitch Filtering Select
28
1
write-only
P29
Peripheral Clock Glitch Filtering Select
29
1
write-only
P3
Peripheral Clock Glitch Filtering Select
3
1
write-only
P30
Peripheral Clock Glitch Filtering Select
30
1
write-only
P31
Peripheral Clock Glitch Filtering Select
31
1
write-only
P4
Peripheral Clock Glitch Filtering Select
4
1
write-only
P5
Peripheral Clock Glitch Filtering Select
5
1
write-only
P6
Peripheral Clock Glitch Filtering Select
6
1
write-only
P7
Peripheral Clock Glitch Filtering Select
7
1
write-only
P8
Peripheral Clock Glitch Filtering Select
8
1
write-only
P9
Peripheral Clock Glitch Filtering Select
9
1
write-only
IFSCER
Input Filter Slow Clock Enable Register
0x84
32
write-only
n
0x0
0x0
P0
Slow Clock Debouncing Filtering Select
0
1
write-only
P1
Slow Clock Debouncing Filtering Select
1
1
write-only
P10
Slow Clock Debouncing Filtering Select
10
1
write-only
P11
Slow Clock Debouncing Filtering Select
11
1
write-only
P12
Slow Clock Debouncing Filtering Select
12
1
write-only
P13
Slow Clock Debouncing Filtering Select
13
1
write-only
P14
Slow Clock Debouncing Filtering Select
14
1
write-only
P15
Slow Clock Debouncing Filtering Select
15
1
write-only
P16
Slow Clock Debouncing Filtering Select
16
1
write-only
P17
Slow Clock Debouncing Filtering Select
17
1
write-only
P18
Slow Clock Debouncing Filtering Select
18
1
write-only
P19
Slow Clock Debouncing Filtering Select
19
1
write-only
P2
Slow Clock Debouncing Filtering Select
2
1
write-only
P20
Slow Clock Debouncing Filtering Select
20
1
write-only
P21
Slow Clock Debouncing Filtering Select
21
1
write-only
P22
Slow Clock Debouncing Filtering Select
22
1
write-only
P23
Slow Clock Debouncing Filtering Select
23
1
write-only
P24
Slow Clock Debouncing Filtering Select
24
1
write-only
P25
Slow Clock Debouncing Filtering Select
25
1
write-only
P26
Slow Clock Debouncing Filtering Select
26
1
write-only
P27
Slow Clock Debouncing Filtering Select
27
1
write-only
P28
Slow Clock Debouncing Filtering Select
28
1
write-only
P29
Slow Clock Debouncing Filtering Select
29
1
write-only
P3
Slow Clock Debouncing Filtering Select
3
1
write-only
P30
Slow Clock Debouncing Filtering Select
30
1
write-only
P31
Slow Clock Debouncing Filtering Select
31
1
write-only
P4
Slow Clock Debouncing Filtering Select
4
1
write-only
P5
Slow Clock Debouncing Filtering Select
5
1
write-only
P6
Slow Clock Debouncing Filtering Select
6
1
write-only
P7
Slow Clock Debouncing Filtering Select
7
1
write-only
P8
Slow Clock Debouncing Filtering Select
8
1
write-only
P9
Slow Clock Debouncing Filtering Select
9
1
write-only
IFSCSR
Input Filter Slow Clock Status Register
0x88
32
read-only
n
0x0
0x0
P0
Glitch or Debouncing Filter Selection Status
0
1
read-only
P1
Glitch or Debouncing Filter Selection Status
1
1
read-only
P10
Glitch or Debouncing Filter Selection Status
10
1
read-only
P11
Glitch or Debouncing Filter Selection Status
11
1
read-only
P12
Glitch or Debouncing Filter Selection Status
12
1
read-only
P13
Glitch or Debouncing Filter Selection Status
13
1
read-only
P14
Glitch or Debouncing Filter Selection Status
14
1
read-only
P15
Glitch or Debouncing Filter Selection Status
15
1
read-only
P16
Glitch or Debouncing Filter Selection Status
16
1
read-only
P17
Glitch or Debouncing Filter Selection Status
17
1
read-only
P18
Glitch or Debouncing Filter Selection Status
18
1
read-only
P19
Glitch or Debouncing Filter Selection Status
19
1
read-only
P2
Glitch or Debouncing Filter Selection Status
2
1
read-only
P20
Glitch or Debouncing Filter Selection Status
20
1
read-only
P21
Glitch or Debouncing Filter Selection Status
21
1
read-only
P22
Glitch or Debouncing Filter Selection Status
22
1
read-only
P23
Glitch or Debouncing Filter Selection Status
23
1
read-only
P24
Glitch or Debouncing Filter Selection Status
24
1
read-only
P25
Glitch or Debouncing Filter Selection Status
25
1
read-only
P26
Glitch or Debouncing Filter Selection Status
26
1
read-only
P27
Glitch or Debouncing Filter Selection Status
27
1
read-only
P28
Glitch or Debouncing Filter Selection Status
28
1
read-only
P29
Glitch or Debouncing Filter Selection Status
29
1
read-only
P3
Glitch or Debouncing Filter Selection Status
3
1
read-only
P30
Glitch or Debouncing Filter Selection Status
30
1
read-only
P31
Glitch or Debouncing Filter Selection Status
31
1
read-only
P4
Glitch or Debouncing Filter Selection Status
4
1
read-only
P5
Glitch or Debouncing Filter Selection Status
5
1
read-only
P6
Glitch or Debouncing Filter Selection Status
6
1
read-only
P7
Glitch or Debouncing Filter Selection Status
7
1
read-only
P8
Glitch or Debouncing Filter Selection Status
8
1
read-only
P9
Glitch or Debouncing Filter Selection Status
9
1
read-only
IFSR
Glitch Input Filter Status Register
0x28
32
read-only
n
0x0
0x0
P0
Input Filer Status
0
1
read-only
P1
Input Filer Status
1
1
read-only
P10
Input Filer Status
10
1
read-only
P11
Input Filer Status
11
1
read-only
P12
Input Filer Status
12
1
read-only
P13
Input Filer Status
13
1
read-only
P14
Input Filer Status
14
1
read-only
P15
Input Filer Status
15
1
read-only
P16
Input Filer Status
16
1
read-only
P17
Input Filer Status
17
1
read-only
P18
Input Filer Status
18
1
read-only
P19
Input Filer Status
19
1
read-only
P2
Input Filer Status
2
1
read-only
P20
Input Filer Status
20
1
read-only
P21
Input Filer Status
21
1
read-only
P22
Input Filer Status
22
1
read-only
P23
Input Filer Status
23
1
read-only
P24
Input Filer Status
24
1
read-only
P25
Input Filer Status
25
1
read-only
P26
Input Filer Status
26
1
read-only
P27
Input Filer Status
27
1
read-only
P28
Input Filer Status
28
1
read-only
P29
Input Filer Status
29
1
read-only
P3
Input Filer Status
3
1
read-only
P30
Input Filer Status
30
1
read-only
P31
Input Filer Status
31
1
read-only
P4
Input Filer Status
4
1
read-only
P5
Input Filer Status
5
1
read-only
P6
Input Filer Status
6
1
read-only
P7
Input Filer Status
7
1
read-only
P8
Input Filer Status
8
1
read-only
P9
Input Filer Status
9
1
read-only
IMR
Interrupt Mask Register
0x48
32
read-only
n
0x0
0x0
P0
Input Change Interrupt Mask
0
1
read-only
P1
Input Change Interrupt Mask
1
1
read-only
P10
Input Change Interrupt Mask
10
1
read-only
P11
Input Change Interrupt Mask
11
1
read-only
P12
Input Change Interrupt Mask
12
1
read-only
P13
Input Change Interrupt Mask
13
1
read-only
P14
Input Change Interrupt Mask
14
1
read-only
P15
Input Change Interrupt Mask
15
1
read-only
P16
Input Change Interrupt Mask
16
1
read-only
P17
Input Change Interrupt Mask
17
1
read-only
P18
Input Change Interrupt Mask
18
1
read-only
P19
Input Change Interrupt Mask
19
1
read-only
P2
Input Change Interrupt Mask
2
1
read-only
P20
Input Change Interrupt Mask
20
1
read-only
P21
Input Change Interrupt Mask
21
1
read-only
P22
Input Change Interrupt Mask
22
1
read-only
P23
Input Change Interrupt Mask
23
1
read-only
P24
Input Change Interrupt Mask
24
1
read-only
P25
Input Change Interrupt Mask
25
1
read-only
P26
Input Change Interrupt Mask
26
1
read-only
P27
Input Change Interrupt Mask
27
1
read-only
P28
Input Change Interrupt Mask
28
1
read-only
P29
Input Change Interrupt Mask
29
1
read-only
P3
Input Change Interrupt Mask
3
1
read-only
P30
Input Change Interrupt Mask
30
1
read-only
P31
Input Change Interrupt Mask
31
1
read-only
P4
Input Change Interrupt Mask
4
1
read-only
P5
Input Change Interrupt Mask
5
1
read-only
P6
Input Change Interrupt Mask
6
1
read-only
P7
Input Change Interrupt Mask
7
1
read-only
P8
Input Change Interrupt Mask
8
1
read-only
P9
Input Change Interrupt Mask
9
1
read-only
ISR
Interrupt Status Register
0x4C
32
read-only
n
0x0
0x0
P0
Input Change Interrupt Status
0
1
read-only
P1
Input Change Interrupt Status
1
1
read-only
P10
Input Change Interrupt Status
10
1
read-only
P11
Input Change Interrupt Status
11
1
read-only
P12
Input Change Interrupt Status
12
1
read-only
P13
Input Change Interrupt Status
13
1
read-only
P14
Input Change Interrupt Status
14
1
read-only
P15
Input Change Interrupt Status
15
1
read-only
P16
Input Change Interrupt Status
16
1
read-only
P17
Input Change Interrupt Status
17
1
read-only
P18
Input Change Interrupt Status
18
1
read-only
P19
Input Change Interrupt Status
19
1
read-only
P2
Input Change Interrupt Status
2
1
read-only
P20
Input Change Interrupt Status
20
1
read-only
P21
Input Change Interrupt Status
21
1
read-only
P22
Input Change Interrupt Status
22
1
read-only
P23
Input Change Interrupt Status
23
1
read-only
P24
Input Change Interrupt Status
24
1
read-only
P25
Input Change Interrupt Status
25
1
read-only
P26
Input Change Interrupt Status
26
1
read-only
P27
Input Change Interrupt Status
27
1
read-only
P28
Input Change Interrupt Status
28
1
read-only
P29
Input Change Interrupt Status
29
1
read-only
P3
Input Change Interrupt Status
3
1
read-only
P30
Input Change Interrupt Status
30
1
read-only
P31
Input Change Interrupt Status
31
1
read-only
P4
Input Change Interrupt Status
4
1
read-only
P5
Input Change Interrupt Status
5
1
read-only
P6
Input Change Interrupt Status
6
1
read-only
P7
Input Change Interrupt Status
7
1
read-only
P8
Input Change Interrupt Status
8
1
read-only
P9
Input Change Interrupt Status
9
1
read-only
LSR
Level Select Register
0xC4
32
write-only
n
0x0
0x0
P0
Level Interrupt Selection
0
1
write-only
P1
Level Interrupt Selection
1
1
write-only
P10
Level Interrupt Selection
10
1
write-only
P11
Level Interrupt Selection
11
1
write-only
P12
Level Interrupt Selection
12
1
write-only
P13
Level Interrupt Selection
13
1
write-only
P14
Level Interrupt Selection
14
1
write-only
P15
Level Interrupt Selection
15
1
write-only
P16
Level Interrupt Selection
16
1
write-only
P17
Level Interrupt Selection
17
1
write-only
P18
Level Interrupt Selection
18
1
write-only
P19
Level Interrupt Selection
19
1
write-only
P2
Level Interrupt Selection
2
1
write-only
P20
Level Interrupt Selection
20
1
write-only
P21
Level Interrupt Selection
21
1
write-only
P22
Level Interrupt Selection
22
1
write-only
P23
Level Interrupt Selection
23
1
write-only
P24
Level Interrupt Selection
24
1
write-only
P25
Level Interrupt Selection
25
1
write-only
P26
Level Interrupt Selection
26
1
write-only
P27
Level Interrupt Selection
27
1
write-only
P28
Level Interrupt Selection
28
1
write-only
P29
Level Interrupt Selection
29
1
write-only
P3
Level Interrupt Selection
3
1
write-only
P30
Level Interrupt Selection
30
1
write-only
P31
Level Interrupt Selection
31
1
write-only
P4
Level Interrupt Selection
4
1
write-only
P5
Level Interrupt Selection
5
1
write-only
P6
Level Interrupt Selection
6
1
write-only
P7
Level Interrupt Selection
7
1
write-only
P8
Level Interrupt Selection
8
1
write-only
P9
Level Interrupt Selection
9
1
write-only
MDDR
Multi-driver Disable Register
0x54
32
write-only
n
0x0
0x0
P0
Multi-drive Disable
0
1
write-only
P1
Multi-drive Disable
1
1
write-only
P10
Multi-drive Disable
10
1
write-only
P11
Multi-drive Disable
11
1
write-only
P12
Multi-drive Disable
12
1
write-only
P13
Multi-drive Disable
13
1
write-only
P14
Multi-drive Disable
14
1
write-only
P15
Multi-drive Disable
15
1
write-only
P16
Multi-drive Disable
16
1
write-only
P17
Multi-drive Disable
17
1
write-only
P18
Multi-drive Disable
18
1
write-only
P19
Multi-drive Disable
19
1
write-only
P2
Multi-drive Disable
2
1
write-only
P20
Multi-drive Disable
20
1
write-only
P21
Multi-drive Disable
21
1
write-only
P22
Multi-drive Disable
22
1
write-only
P23
Multi-drive Disable
23
1
write-only
P24
Multi-drive Disable
24
1
write-only
P25
Multi-drive Disable
25
1
write-only
P26
Multi-drive Disable
26
1
write-only
P27
Multi-drive Disable
27
1
write-only
P28
Multi-drive Disable
28
1
write-only
P29
Multi-drive Disable
29
1
write-only
P3
Multi-drive Disable
3
1
write-only
P30
Multi-drive Disable
30
1
write-only
P31
Multi-drive Disable
31
1
write-only
P4
Multi-drive Disable
4
1
write-only
P5
Multi-drive Disable
5
1
write-only
P6
Multi-drive Disable
6
1
write-only
P7
Multi-drive Disable
7
1
write-only
P8
Multi-drive Disable
8
1
write-only
P9
Multi-drive Disable
9
1
write-only
MDER
Multi-driver Enable Register
0x50
32
write-only
n
0x0
0x0
P0
Multi-drive Enable
0
1
write-only
P1
Multi-drive Enable
1
1
write-only
P10
Multi-drive Enable
10
1
write-only
P11
Multi-drive Enable
11
1
write-only
P12
Multi-drive Enable
12
1
write-only
P13
Multi-drive Enable
13
1
write-only
P14
Multi-drive Enable
14
1
write-only
P15
Multi-drive Enable
15
1
write-only
P16
Multi-drive Enable
16
1
write-only
P17
Multi-drive Enable
17
1
write-only
P18
Multi-drive Enable
18
1
write-only
P19
Multi-drive Enable
19
1
write-only
P2
Multi-drive Enable
2
1
write-only
P20
Multi-drive Enable
20
1
write-only
P21
Multi-drive Enable
21
1
write-only
P22
Multi-drive Enable
22
1
write-only
P23
Multi-drive Enable
23
1
write-only
P24
Multi-drive Enable
24
1
write-only
P25
Multi-drive Enable
25
1
write-only
P26
Multi-drive Enable
26
1
write-only
P27
Multi-drive Enable
27
1
write-only
P28
Multi-drive Enable
28
1
write-only
P29
Multi-drive Enable
29
1
write-only
P3
Multi-drive Enable
3
1
write-only
P30
Multi-drive Enable
30
1
write-only
P31
Multi-drive Enable
31
1
write-only
P4
Multi-drive Enable
4
1
write-only
P5
Multi-drive Enable
5
1
write-only
P6
Multi-drive Enable
6
1
write-only
P7
Multi-drive Enable
7
1
write-only
P8
Multi-drive Enable
8
1
write-only
P9
Multi-drive Enable
9
1
write-only
MDSR
Multi-driver Status Register
0x58
32
read-only
n
0x0
0x0
P0
Multi-drive Status
0
1
read-only
P1
Multi-drive Status
1
1
read-only
P10
Multi-drive Status
10
1
read-only
P11
Multi-drive Status
11
1
read-only
P12
Multi-drive Status
12
1
read-only
P13
Multi-drive Status
13
1
read-only
P14
Multi-drive Status
14
1
read-only
P15
Multi-drive Status
15
1
read-only
P16
Multi-drive Status
16
1
read-only
P17
Multi-drive Status
17
1
read-only
P18
Multi-drive Status
18
1
read-only
P19
Multi-drive Status
19
1
read-only
P2
Multi-drive Status
2
1
read-only
P20
Multi-drive Status
20
1
read-only
P21
Multi-drive Status
21
1
read-only
P22
Multi-drive Status
22
1
read-only
P23
Multi-drive Status
23
1
read-only
P24
Multi-drive Status
24
1
read-only
P25
Multi-drive Status
25
1
read-only
P26
Multi-drive Status
26
1
read-only
P27
Multi-drive Status
27
1
read-only
P28
Multi-drive Status
28
1
read-only
P29
Multi-drive Status
29
1
read-only
P3
Multi-drive Status
3
1
read-only
P30
Multi-drive Status
30
1
read-only
P31
Multi-drive Status
31
1
read-only
P4
Multi-drive Status
4
1
read-only
P5
Multi-drive Status
5
1
read-only
P6
Multi-drive Status
6
1
read-only
P7
Multi-drive Status
7
1
read-only
P8
Multi-drive Status
8
1
read-only
P9
Multi-drive Status
9
1
read-only
ODR
Output Disable Register
0x14
32
write-only
n
0x0
0x0
P0
Output Disable
0
1
write-only
P1
Output Disable
1
1
write-only
P10
Output Disable
10
1
write-only
P11
Output Disable
11
1
write-only
P12
Output Disable
12
1
write-only
P13
Output Disable
13
1
write-only
P14
Output Disable
14
1
write-only
P15
Output Disable
15
1
write-only
P16
Output Disable
16
1
write-only
P17
Output Disable
17
1
write-only
P18
Output Disable
18
1
write-only
P19
Output Disable
19
1
write-only
P2
Output Disable
2
1
write-only
P20
Output Disable
20
1
write-only
P21
Output Disable
21
1
write-only
P22
Output Disable
22
1
write-only
P23
Output Disable
23
1
write-only
P24
Output Disable
24
1
write-only
P25
Output Disable
25
1
write-only
P26
Output Disable
26
1
write-only
P27
Output Disable
27
1
write-only
P28
Output Disable
28
1
write-only
P29
Output Disable
29
1
write-only
P3
Output Disable
3
1
write-only
P30
Output Disable
30
1
write-only
P31
Output Disable
31
1
write-only
P4
Output Disable
4
1
write-only
P5
Output Disable
5
1
write-only
P6
Output Disable
6
1
write-only
P7
Output Disable
7
1
write-only
P8
Output Disable
8
1
write-only
P9
Output Disable
9
1
write-only
ODSR
Output Data Status Register
0x38
32
read-write
n
0x0
0x0
P0
Output Data Status
0
1
read-write
P1
Output Data Status
1
1
read-write
P10
Output Data Status
10
1
read-write
P11
Output Data Status
11
1
read-write
P12
Output Data Status
12
1
read-write
P13
Output Data Status
13
1
read-write
P14
Output Data Status
14
1
read-write
P15
Output Data Status
15
1
read-write
P16
Output Data Status
16
1
read-write
P17
Output Data Status
17
1
read-write
P18
Output Data Status
18
1
read-write
P19
Output Data Status
19
1
read-write
P2
Output Data Status
2
1
read-write
P20
Output Data Status
20
1
read-write
P21
Output Data Status
21
1
read-write
P22
Output Data Status
22
1
read-write
P23
Output Data Status
23
1
read-write
P24
Output Data Status
24
1
read-write
P25
Output Data Status
25
1
read-write
P26
Output Data Status
26
1
read-write
P27
Output Data Status
27
1
read-write
P28
Output Data Status
28
1
read-write
P29
Output Data Status
29
1
read-write
P3
Output Data Status
3
1
read-write
P30
Output Data Status
30
1
read-write
P31
Output Data Status
31
1
read-write
P4
Output Data Status
4
1
read-write
P5
Output Data Status
5
1
read-write
P6
Output Data Status
6
1
read-write
P7
Output Data Status
7
1
read-write
P8
Output Data Status
8
1
read-write
P9
Output Data Status
9
1
read-write
OER
Output Enable Register
0x10
32
write-only
n
0x0
0x0
P0
Output Enable
0
1
write-only
P1
Output Enable
1
1
write-only
P10
Output Enable
10
1
write-only
P11
Output Enable
11
1
write-only
P12
Output Enable
12
1
write-only
P13
Output Enable
13
1
write-only
P14
Output Enable
14
1
write-only
P15
Output Enable
15
1
write-only
P16
Output Enable
16
1
write-only
P17
Output Enable
17
1
write-only
P18
Output Enable
18
1
write-only
P19
Output Enable
19
1
write-only
P2
Output Enable
2
1
write-only
P20
Output Enable
20
1
write-only
P21
Output Enable
21
1
write-only
P22
Output Enable
22
1
write-only
P23
Output Enable
23
1
write-only
P24
Output Enable
24
1
write-only
P25
Output Enable
25
1
write-only
P26
Output Enable
26
1
write-only
P27
Output Enable
27
1
write-only
P28
Output Enable
28
1
write-only
P29
Output Enable
29
1
write-only
P3
Output Enable
3
1
write-only
P30
Output Enable
30
1
write-only
P31
Output Enable
31
1
write-only
P4
Output Enable
4
1
write-only
P5
Output Enable
5
1
write-only
P6
Output Enable
6
1
write-only
P7
Output Enable
7
1
write-only
P8
Output Enable
8
1
write-only
P9
Output Enable
9
1
write-only
OSR
Output Status Register
0x18
32
read-only
n
0x0
0x0
P0
Output Status
0
1
read-only
P1
Output Status
1
1
read-only
P10
Output Status
10
1
read-only
P11
Output Status
11
1
read-only
P12
Output Status
12
1
read-only
P13
Output Status
13
1
read-only
P14
Output Status
14
1
read-only
P15
Output Status
15
1
read-only
P16
Output Status
16
1
read-only
P17
Output Status
17
1
read-only
P18
Output Status
18
1
read-only
P19
Output Status
19
1
read-only
P2
Output Status
2
1
read-only
P20
Output Status
20
1
read-only
P21
Output Status
21
1
read-only
P22
Output Status
22
1
read-only
P23
Output Status
23
1
read-only
P24
Output Status
24
1
read-only
P25
Output Status
25
1
read-only
P26
Output Status
26
1
read-only
P27
Output Status
27
1
read-only
P28
Output Status
28
1
read-only
P29
Output Status
29
1
read-only
P3
Output Status
3
1
read-only
P30
Output Status
30
1
read-only
P31
Output Status
31
1
read-only
P4
Output Status
4
1
read-only
P5
Output Status
5
1
read-only
P6
Output Status
6
1
read-only
P7
Output Status
7
1
read-only
P8
Output Status
8
1
read-only
P9
Output Status
9
1
read-only
OWDR
Output Write Disable
0xA4
32
write-only
n
0x0
0x0
P0
Output Write Disable
0
1
write-only
P1
Output Write Disable
1
1
write-only
P10
Output Write Disable
10
1
write-only
P11
Output Write Disable
11
1
write-only
P12
Output Write Disable
12
1
write-only
P13
Output Write Disable
13
1
write-only
P14
Output Write Disable
14
1
write-only
P15
Output Write Disable
15
1
write-only
P16
Output Write Disable
16
1
write-only
P17
Output Write Disable
17
1
write-only
P18
Output Write Disable
18
1
write-only
P19
Output Write Disable
19
1
write-only
P2
Output Write Disable
2
1
write-only
P20
Output Write Disable
20
1
write-only
P21
Output Write Disable
21
1
write-only
P22
Output Write Disable
22
1
write-only
P23
Output Write Disable
23
1
write-only
P24
Output Write Disable
24
1
write-only
P25
Output Write Disable
25
1
write-only
P26
Output Write Disable
26
1
write-only
P27
Output Write Disable
27
1
write-only
P28
Output Write Disable
28
1
write-only
P29
Output Write Disable
29
1
write-only
P3
Output Write Disable
3
1
write-only
P30
Output Write Disable
30
1
write-only
P31
Output Write Disable
31
1
write-only
P4
Output Write Disable
4
1
write-only
P5
Output Write Disable
5
1
write-only
P6
Output Write Disable
6
1
write-only
P7
Output Write Disable
7
1
write-only
P8
Output Write Disable
8
1
write-only
P9
Output Write Disable
9
1
write-only
OWER
Output Write Enable
0xA0
32
write-only
n
0x0
0x0
P0
Output Write Enable
0
1
write-only
P1
Output Write Enable
1
1
write-only
P10
Output Write Enable
10
1
write-only
P11
Output Write Enable
11
1
write-only
P12
Output Write Enable
12
1
write-only
P13
Output Write Enable
13
1
write-only
P14
Output Write Enable
14
1
write-only
P15
Output Write Enable
15
1
write-only
P16
Output Write Enable
16
1
write-only
P17
Output Write Enable
17
1
write-only
P18
Output Write Enable
18
1
write-only
P19
Output Write Enable
19
1
write-only
P2
Output Write Enable
2
1
write-only
P20
Output Write Enable
20
1
write-only
P21
Output Write Enable
21
1
write-only
P22
Output Write Enable
22
1
write-only
P23
Output Write Enable
23
1
write-only
P24
Output Write Enable
24
1
write-only
P25
Output Write Enable
25
1
write-only
P26
Output Write Enable
26
1
write-only
P27
Output Write Enable
27
1
write-only
P28
Output Write Enable
28
1
write-only
P29
Output Write Enable
29
1
write-only
P3
Output Write Enable
3
1
write-only
P30
Output Write Enable
30
1
write-only
P31
Output Write Enable
31
1
write-only
P4
Output Write Enable
4
1
write-only
P5
Output Write Enable
5
1
write-only
P6
Output Write Enable
6
1
write-only
P7
Output Write Enable
7
1
write-only
P8
Output Write Enable
8
1
write-only
P9
Output Write Enable
9
1
write-only
OWSR
Output Write Status Register
0xA8
32
read-only
n
0x0
0x0
P0
Output Write Status
0
1
read-only
P1
Output Write Status
1
1
read-only
P10
Output Write Status
10
1
read-only
P11
Output Write Status
11
1
read-only
P12
Output Write Status
12
1
read-only
P13
Output Write Status
13
1
read-only
P14
Output Write Status
14
1
read-only
P15
Output Write Status
15
1
read-only
P16
Output Write Status
16
1
read-only
P17
Output Write Status
17
1
read-only
P18
Output Write Status
18
1
read-only
P19
Output Write Status
19
1
read-only
P2
Output Write Status
2
1
read-only
P20
Output Write Status
20
1
read-only
P21
Output Write Status
21
1
read-only
P22
Output Write Status
22
1
read-only
P23
Output Write Status
23
1
read-only
P24
Output Write Status
24
1
read-only
P25
Output Write Status
25
1
read-only
P26
Output Write Status
26
1
read-only
P27
Output Write Status
27
1
read-only
P28
Output Write Status
28
1
read-only
P29
Output Write Status
29
1
read-only
P3
Output Write Status
3
1
read-only
P30
Output Write Status
30
1
read-only
P31
Output Write Status
31
1
read-only
P4
Output Write Status
4
1
read-only
P5
Output Write Status
5
1
read-only
P6
Output Write Status
6
1
read-only
P7
Output Write Status
7
1
read-only
P8
Output Write Status
8
1
read-only
P9
Output Write Status
9
1
read-only
PDR
PIO Disable Register
0x4
32
write-only
n
0x0
0x0
P0
PIO Disable
0
1
write-only
P1
PIO Disable
1
1
write-only
P10
PIO Disable
10
1
write-only
P11
PIO Disable
11
1
write-only
P12
PIO Disable
12
1
write-only
P13
PIO Disable
13
1
write-only
P14
PIO Disable
14
1
write-only
P15
PIO Disable
15
1
write-only
P16
PIO Disable
16
1
write-only
P17
PIO Disable
17
1
write-only
P18
PIO Disable
18
1
write-only
P19
PIO Disable
19
1
write-only
P2
PIO Disable
2
1
write-only
P20
PIO Disable
20
1
write-only
P21
PIO Disable
21
1
write-only
P22
PIO Disable
22
1
write-only
P23
PIO Disable
23
1
write-only
P24
PIO Disable
24
1
write-only
P25
PIO Disable
25
1
write-only
P26
PIO Disable
26
1
write-only
P27
PIO Disable
27
1
write-only
P28
PIO Disable
28
1
write-only
P29
PIO Disable
29
1
write-only
P3
PIO Disable
3
1
write-only
P30
PIO Disable
30
1
write-only
P31
PIO Disable
31
1
write-only
P4
PIO Disable
4
1
write-only
P5
PIO Disable
5
1
write-only
P6
PIO Disable
6
1
write-only
P7
PIO Disable
7
1
write-only
P8
PIO Disable
8
1
write-only
P9
PIO Disable
9
1
write-only
PDSR
Pin Data Status Register
0x3C
32
read-only
n
0x0
0x0
P0
Output Data Status
0
1
read-only
P1
Output Data Status
1
1
read-only
P10
Output Data Status
10
1
read-only
P11
Output Data Status
11
1
read-only
P12
Output Data Status
12
1
read-only
P13
Output Data Status
13
1
read-only
P14
Output Data Status
14
1
read-only
P15
Output Data Status
15
1
read-only
P16
Output Data Status
16
1
read-only
P17
Output Data Status
17
1
read-only
P18
Output Data Status
18
1
read-only
P19
Output Data Status
19
1
read-only
P2
Output Data Status
2
1
read-only
P20
Output Data Status
20
1
read-only
P21
Output Data Status
21
1
read-only
P22
Output Data Status
22
1
read-only
P23
Output Data Status
23
1
read-only
P24
Output Data Status
24
1
read-only
P25
Output Data Status
25
1
read-only
P26
Output Data Status
26
1
read-only
P27
Output Data Status
27
1
read-only
P28
Output Data Status
28
1
read-only
P29
Output Data Status
29
1
read-only
P3
Output Data Status
3
1
read-only
P30
Output Data Status
30
1
read-only
P31
Output Data Status
31
1
read-only
P4
Output Data Status
4
1
read-only
P5
Output Data Status
5
1
read-only
P6
Output Data Status
6
1
read-only
P7
Output Data Status
7
1
read-only
P8
Output Data Status
8
1
read-only
P9
Output Data Status
9
1
read-only
PER
PIO Enable Register
0x0
32
write-only
n
0x0
0x0
P0
PIO Enable
0
1
write-only
P1
PIO Enable
1
1
write-only
P10
PIO Enable
10
1
write-only
P11
PIO Enable
11
1
write-only
P12
PIO Enable
12
1
write-only
P13
PIO Enable
13
1
write-only
P14
PIO Enable
14
1
write-only
P15
PIO Enable
15
1
write-only
P16
PIO Enable
16
1
write-only
P17
PIO Enable
17
1
write-only
P18
PIO Enable
18
1
write-only
P19
PIO Enable
19
1
write-only
P2
PIO Enable
2
1
write-only
P20
PIO Enable
20
1
write-only
P21
PIO Enable
21
1
write-only
P22
PIO Enable
22
1
write-only
P23
PIO Enable
23
1
write-only
P24
PIO Enable
24
1
write-only
P25
PIO Enable
25
1
write-only
P26
PIO Enable
26
1
write-only
P27
PIO Enable
27
1
write-only
P28
PIO Enable
28
1
write-only
P29
PIO Enable
29
1
write-only
P3
PIO Enable
3
1
write-only
P30
PIO Enable
30
1
write-only
P31
PIO Enable
31
1
write-only
P4
PIO Enable
4
1
write-only
P5
PIO Enable
5
1
write-only
P6
PIO Enable
6
1
write-only
P7
PIO Enable
7
1
write-only
P8
PIO Enable
8
1
write-only
P9
PIO Enable
9
1
write-only
PPDDR
Pad Pull-down Disable Register
0x90
32
write-only
n
0x0
0x0
P0
Pull-Down Disable
0
1
write-only
P1
Pull-Down Disable
1
1
write-only
P10
Pull-Down Disable
10
1
write-only
P11
Pull-Down Disable
11
1
write-only
P12
Pull-Down Disable
12
1
write-only
P13
Pull-Down Disable
13
1
write-only
P14
Pull-Down Disable
14
1
write-only
P15
Pull-Down Disable
15
1
write-only
P16
Pull-Down Disable
16
1
write-only
P17
Pull-Down Disable
17
1
write-only
P18
Pull-Down Disable
18
1
write-only
P19
Pull-Down Disable
19
1
write-only
P2
Pull-Down Disable
2
1
write-only
P20
Pull-Down Disable
20
1
write-only
P21
Pull-Down Disable
21
1
write-only
P22
Pull-Down Disable
22
1
write-only
P23
Pull-Down Disable
23
1
write-only
P24
Pull-Down Disable
24
1
write-only
P25
Pull-Down Disable
25
1
write-only
P26
Pull-Down Disable
26
1
write-only
P27
Pull-Down Disable
27
1
write-only
P28
Pull-Down Disable
28
1
write-only
P29
Pull-Down Disable
29
1
write-only
P3
Pull-Down Disable
3
1
write-only
P30
Pull-Down Disable
30
1
write-only
P31
Pull-Down Disable
31
1
write-only
P4
Pull-Down Disable
4
1
write-only
P5
Pull-Down Disable
5
1
write-only
P6
Pull-Down Disable
6
1
write-only
P7
Pull-Down Disable
7
1
write-only
P8
Pull-Down Disable
8
1
write-only
P9
Pull-Down Disable
9
1
write-only
PPDER
Pad Pull-down Enable Register
0x94
32
write-only
n
0x0
0x0
P0
Pull-Down Enable
0
1
write-only
P1
Pull-Down Enable
1
1
write-only
P10
Pull-Down Enable
10
1
write-only
P11
Pull-Down Enable
11
1
write-only
P12
Pull-Down Enable
12
1
write-only
P13
Pull-Down Enable
13
1
write-only
P14
Pull-Down Enable
14
1
write-only
P15
Pull-Down Enable
15
1
write-only
P16
Pull-Down Enable
16
1
write-only
P17
Pull-Down Enable
17
1
write-only
P18
Pull-Down Enable
18
1
write-only
P19
Pull-Down Enable
19
1
write-only
P2
Pull-Down Enable
2
1
write-only
P20
Pull-Down Enable
20
1
write-only
P21
Pull-Down Enable
21
1
write-only
P22
Pull-Down Enable
22
1
write-only
P23
Pull-Down Enable
23
1
write-only
P24
Pull-Down Enable
24
1
write-only
P25
Pull-Down Enable
25
1
write-only
P26
Pull-Down Enable
26
1
write-only
P27
Pull-Down Enable
27
1
write-only
P28
Pull-Down Enable
28
1
write-only
P29
Pull-Down Enable
29
1
write-only
P3
Pull-Down Enable
3
1
write-only
P30
Pull-Down Enable
30
1
write-only
P31
Pull-Down Enable
31
1
write-only
P4
Pull-Down Enable
4
1
write-only
P5
Pull-Down Enable
5
1
write-only
P6
Pull-Down Enable
6
1
write-only
P7
Pull-Down Enable
7
1
write-only
P8
Pull-Down Enable
8
1
write-only
P9
Pull-Down Enable
9
1
write-only
PPDSR
Pad Pull-down Status Register
0x98
32
read-only
n
0x0
0x0
P0
Pull-Down Status
0
1
read-only
P1
Pull-Down Status
1
1
read-only
P10
Pull-Down Status
10
1
read-only
P11
Pull-Down Status
11
1
read-only
P12
Pull-Down Status
12
1
read-only
P13
Pull-Down Status
13
1
read-only
P14
Pull-Down Status
14
1
read-only
P15
Pull-Down Status
15
1
read-only
P16
Pull-Down Status
16
1
read-only
P17
Pull-Down Status
17
1
read-only
P18
Pull-Down Status
18
1
read-only
P19
Pull-Down Status
19
1
read-only
P2
Pull-Down Status
2
1
read-only
P20
Pull-Down Status
20
1
read-only
P21
Pull-Down Status
21
1
read-only
P22
Pull-Down Status
22
1
read-only
P23
Pull-Down Status
23
1
read-only
P24
Pull-Down Status
24
1
read-only
P25
Pull-Down Status
25
1
read-only
P26
Pull-Down Status
26
1
read-only
P27
Pull-Down Status
27
1
read-only
P28
Pull-Down Status
28
1
read-only
P29
Pull-Down Status
29
1
read-only
P3
Pull-Down Status
3
1
read-only
P30
Pull-Down Status
30
1
read-only
P31
Pull-Down Status
31
1
read-only
P4
Pull-Down Status
4
1
read-only
P5
Pull-Down Status
5
1
read-only
P6
Pull-Down Status
6
1
read-only
P7
Pull-Down Status
7
1
read-only
P8
Pull-Down Status
8
1
read-only
P9
Pull-Down Status
9
1
read-only
PSR
PIO Status Register
0x8
32
read-only
n
0x0
0x0
P0
PIO Status
0
1
read-only
P1
PIO Status
1
1
read-only
P10
PIO Status
10
1
read-only
P11
PIO Status
11
1
read-only
P12
PIO Status
12
1
read-only
P13
PIO Status
13
1
read-only
P14
PIO Status
14
1
read-only
P15
PIO Status
15
1
read-only
P16
PIO Status
16
1
read-only
P17
PIO Status
17
1
read-only
P18
PIO Status
18
1
read-only
P19
PIO Status
19
1
read-only
P2
PIO Status
2
1
read-only
P20
PIO Status
20
1
read-only
P21
PIO Status
21
1
read-only
P22
PIO Status
22
1
read-only
P23
PIO Status
23
1
read-only
P24
PIO Status
24
1
read-only
P25
PIO Status
25
1
read-only
P26
PIO Status
26
1
read-only
P27
PIO Status
27
1
read-only
P28
PIO Status
28
1
read-only
P29
PIO Status
29
1
read-only
P3
PIO Status
3
1
read-only
P30
PIO Status
30
1
read-only
P31
PIO Status
31
1
read-only
P4
PIO Status
4
1
read-only
P5
PIO Status
5
1
read-only
P6
PIO Status
6
1
read-only
P7
PIO Status
7
1
read-only
P8
PIO Status
8
1
read-only
P9
PIO Status
9
1
read-only
PUDR
Pull-up Disable Register
0x60
32
write-only
n
0x0
0x0
P0
Pull-Up Disable
0
1
write-only
P1
Pull-Up Disable
1
1
write-only
P10
Pull-Up Disable
10
1
write-only
P11
Pull-Up Disable
11
1
write-only
P12
Pull-Up Disable
12
1
write-only
P13
Pull-Up Disable
13
1
write-only
P14
Pull-Up Disable
14
1
write-only
P15
Pull-Up Disable
15
1
write-only
P16
Pull-Up Disable
16
1
write-only
P17
Pull-Up Disable
17
1
write-only
P18
Pull-Up Disable
18
1
write-only
P19
Pull-Up Disable
19
1
write-only
P2
Pull-Up Disable
2
1
write-only
P20
Pull-Up Disable
20
1
write-only
P21
Pull-Up Disable
21
1
write-only
P22
Pull-Up Disable
22
1
write-only
P23
Pull-Up Disable
23
1
write-only
P24
Pull-Up Disable
24
1
write-only
P25
Pull-Up Disable
25
1
write-only
P26
Pull-Up Disable
26
1
write-only
P27
Pull-Up Disable
27
1
write-only
P28
Pull-Up Disable
28
1
write-only
P29
Pull-Up Disable
29
1
write-only
P3
Pull-Up Disable
3
1
write-only
P30
Pull-Up Disable
30
1
write-only
P31
Pull-Up Disable
31
1
write-only
P4
Pull-Up Disable
4
1
write-only
P5
Pull-Up Disable
5
1
write-only
P6
Pull-Up Disable
6
1
write-only
P7
Pull-Up Disable
7
1
write-only
P8
Pull-Up Disable
8
1
write-only
P9
Pull-Up Disable
9
1
write-only
PUER
Pull-up Enable Register
0x64
32
write-only
n
0x0
0x0
P0
Pull-Up Enable
0
1
write-only
P1
Pull-Up Enable
1
1
write-only
P10
Pull-Up Enable
10
1
write-only
P11
Pull-Up Enable
11
1
write-only
P12
Pull-Up Enable
12
1
write-only
P13
Pull-Up Enable
13
1
write-only
P14
Pull-Up Enable
14
1
write-only
P15
Pull-Up Enable
15
1
write-only
P16
Pull-Up Enable
16
1
write-only
P17
Pull-Up Enable
17
1
write-only
P18
Pull-Up Enable
18
1
write-only
P19
Pull-Up Enable
19
1
write-only
P2
Pull-Up Enable
2
1
write-only
P20
Pull-Up Enable
20
1
write-only
P21
Pull-Up Enable
21
1
write-only
P22
Pull-Up Enable
22
1
write-only
P23
Pull-Up Enable
23
1
write-only
P24
Pull-Up Enable
24
1
write-only
P25
Pull-Up Enable
25
1
write-only
P26
Pull-Up Enable
26
1
write-only
P27
Pull-Up Enable
27
1
write-only
P28
Pull-Up Enable
28
1
write-only
P29
Pull-Up Enable
29
1
write-only
P3
Pull-Up Enable
3
1
write-only
P30
Pull-Up Enable
30
1
write-only
P31
Pull-Up Enable
31
1
write-only
P4
Pull-Up Enable
4
1
write-only
P5
Pull-Up Enable
5
1
write-only
P6
Pull-Up Enable
6
1
write-only
P7
Pull-Up Enable
7
1
write-only
P8
Pull-Up Enable
8
1
write-only
P9
Pull-Up Enable
9
1
write-only
PUSR
Pad Pull-up Status Register
0x68
32
read-only
n
0x0
0x0
P0
Pull-Up Status
0
1
read-only
P1
Pull-Up Status
1
1
read-only
P10
Pull-Up Status
10
1
read-only
P11
Pull-Up Status
11
1
read-only
P12
Pull-Up Status
12
1
read-only
P13
Pull-Up Status
13
1
read-only
P14
Pull-Up Status
14
1
read-only
P15
Pull-Up Status
15
1
read-only
P16
Pull-Up Status
16
1
read-only
P17
Pull-Up Status
17
1
read-only
P18
Pull-Up Status
18
1
read-only
P19
Pull-Up Status
19
1
read-only
P2
Pull-Up Status
2
1
read-only
P20
Pull-Up Status
20
1
read-only
P21
Pull-Up Status
21
1
read-only
P22
Pull-Up Status
22
1
read-only
P23
Pull-Up Status
23
1
read-only
P24
Pull-Up Status
24
1
read-only
P25
Pull-Up Status
25
1
read-only
P26
Pull-Up Status
26
1
read-only
P27
Pull-Up Status
27
1
read-only
P28
Pull-Up Status
28
1
read-only
P29
Pull-Up Status
29
1
read-only
P3
Pull-Up Status
3
1
read-only
P30
Pull-Up Status
30
1
read-only
P31
Pull-Up Status
31
1
read-only
P4
Pull-Up Status
4
1
read-only
P5
Pull-Up Status
5
1
read-only
P6
Pull-Up Status
6
1
read-only
P7
Pull-Up Status
7
1
read-only
P8
Pull-Up Status
8
1
read-only
P9
Pull-Up Status
9
1
read-only
REHLSR
Rising Edge/High-Level Select Register
0xD4
32
write-only
n
0x0
0x0
P0
Rising Edge/High-Level Interrupt Selection
0
1
write-only
P1
Rising Edge/High-Level Interrupt Selection
1
1
write-only
P10
Rising Edge/High-Level Interrupt Selection
10
1
write-only
P11
Rising Edge/High-Level Interrupt Selection
11
1
write-only
P12
Rising Edge/High-Level Interrupt Selection
12
1
write-only
P13
Rising Edge/High-Level Interrupt Selection
13
1
write-only
P14
Rising Edge/High-Level Interrupt Selection
14
1
write-only
P15
Rising Edge/High-Level Interrupt Selection
15
1
write-only
P16
Rising Edge/High-Level Interrupt Selection
16
1
write-only
P17
Rising Edge/High-Level Interrupt Selection
17
1
write-only
P18
Rising Edge/High-Level Interrupt Selection
18
1
write-only
P19
Rising Edge/High-Level Interrupt Selection
19
1
write-only
P2
Rising Edge/High-Level Interrupt Selection
2
1
write-only
P20
Rising Edge/High-Level Interrupt Selection
20
1
write-only
P21
Rising Edge/High-Level Interrupt Selection
21
1
write-only
P22
Rising Edge/High-Level Interrupt Selection
22
1
write-only
P23
Rising Edge/High-Level Interrupt Selection
23
1
write-only
P24
Rising Edge/High-Level Interrupt Selection
24
1
write-only
P25
Rising Edge/High-Level Interrupt Selection
25
1
write-only
P26
Rising Edge/High-Level Interrupt Selection
26
1
write-only
P27
Rising Edge/High-Level Interrupt Selection
27
1
write-only
P28
Rising Edge/High-Level Interrupt Selection
28
1
write-only
P29
Rising Edge/High-Level Interrupt Selection
29
1
write-only
P3
Rising Edge/High-Level Interrupt Selection
3
1
write-only
P30
Rising Edge/High-Level Interrupt Selection
30
1
write-only
P31
Rising Edge/High-Level Interrupt Selection
31
1
write-only
P4
Rising Edge/High-Level Interrupt Selection
4
1
write-only
P5
Rising Edge/High-Level Interrupt Selection
5
1
write-only
P6
Rising Edge/High-Level Interrupt Selection
6
1
write-only
P7
Rising Edge/High-Level Interrupt Selection
7
1
write-only
P8
Rising Edge/High-Level Interrupt Selection
8
1
write-only
P9
Rising Edge/High-Level Interrupt Selection
9
1
write-only
SCDR
Slow Clock Divider Debouncing Register
0x8C
32
read-write
n
0x0
0x0
DIV
Slow Clock Divider Selection for Debouncing
0
14
read-write
SCHMITT
Schmitt Trigger Register
0x100
32
read-write
n
0x0
0x0
SCHMITT0
Schmitt Trigger Control
0
1
read-write
SCHMITT1
Schmitt Trigger Control
1
1
read-write
SCHMITT10
Schmitt Trigger Control
10
1
read-write
SCHMITT11
Schmitt Trigger Control
11
1
read-write
SCHMITT12
Schmitt Trigger Control
12
1
read-write
SCHMITT13
Schmitt Trigger Control
13
1
read-write
SCHMITT14
Schmitt Trigger Control
14
1
read-write
SCHMITT15
Schmitt Trigger Control
15
1
read-write
SCHMITT16
Schmitt Trigger Control
16
1
read-write
SCHMITT17
Schmitt Trigger Control
17
1
read-write
SCHMITT18
Schmitt Trigger Control
18
1
read-write
SCHMITT19
Schmitt Trigger Control
19
1
read-write
SCHMITT2
Schmitt Trigger Control
2
1
read-write
SCHMITT20
Schmitt Trigger Control
20
1
read-write
SCHMITT21
Schmitt Trigger Control
21
1
read-write
SCHMITT22
Schmitt Trigger Control
22
1
read-write
SCHMITT23
Schmitt Trigger Control
23
1
read-write
SCHMITT24
Schmitt Trigger Control
24
1
read-write
SCHMITT25
Schmitt Trigger Control
25
1
read-write
SCHMITT26
Schmitt Trigger Control
26
1
read-write
SCHMITT27
Schmitt Trigger Control
27
1
read-write
SCHMITT28
Schmitt Trigger Control
28
1
read-write
SCHMITT29
Schmitt Trigger Control
29
1
read-write
SCHMITT3
Schmitt Trigger Control
3
1
read-write
SCHMITT30
Schmitt Trigger Control
30
1
read-write
SCHMITT31
Schmitt Trigger Control
31
1
read-write
SCHMITT4
Schmitt Trigger Control
4
1
read-write
SCHMITT5
Schmitt Trigger Control
5
1
read-write
SCHMITT6
Schmitt Trigger Control
6
1
read-write
SCHMITT7
Schmitt Trigger Control
7
1
read-write
SCHMITT8
Schmitt Trigger Control
8
1
read-write
SCHMITT9
Schmitt Trigger Control
9
1
read-write
SODR
Set Output Data Register
0x30
32
write-only
n
0x0
0x0
P0
Set Output Data
0
1
write-only
P1
Set Output Data
1
1
write-only
P10
Set Output Data
10
1
write-only
P11
Set Output Data
11
1
write-only
P12
Set Output Data
12
1
write-only
P13
Set Output Data
13
1
write-only
P14
Set Output Data
14
1
write-only
P15
Set Output Data
15
1
write-only
P16
Set Output Data
16
1
write-only
P17
Set Output Data
17
1
write-only
P18
Set Output Data
18
1
write-only
P19
Set Output Data
19
1
write-only
P2
Set Output Data
2
1
write-only
P20
Set Output Data
20
1
write-only
P21
Set Output Data
21
1
write-only
P22
Set Output Data
22
1
write-only
P23
Set Output Data
23
1
write-only
P24
Set Output Data
24
1
write-only
P25
Set Output Data
25
1
write-only
P26
Set Output Data
26
1
write-only
P27
Set Output Data
27
1
write-only
P28
Set Output Data
28
1
write-only
P29
Set Output Data
29
1
write-only
P3
Set Output Data
3
1
write-only
P30
Set Output Data
30
1
write-only
P31
Set Output Data
31
1
write-only
P4
Set Output Data
4
1
write-only
P5
Set Output Data
5
1
write-only
P6
Set Output Data
6
1
write-only
P7
Set Output Data
7
1
write-only
P8
Set Output Data
8
1
write-only
P9
Set Output Data
9
1
write-only
WPMR
Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protection Enable
0
1
read-write
WPKEY
Write Protection Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
0x50494F
WPSR
Write Protection Status Register
0xE8
32
read-only
n
0x0
0x0
WPVS
Write Protection Violation Status
0
1
read-only
WPVSRC
Write Protection Violation Source
8
16
read-only
PIOB
Parallel Input/Output Controller B
PIO
0x0
0x0
0x200
registers
n
PIOB
12
ABCDSR0
Peripheral Select Register
0x70
32
read-write
n
P0
Peripheral Select
0
1
read-write
P1
Peripheral Select
1
1
read-write
P10
Peripheral Select
10
1
read-write
P11
Peripheral Select
11
1
read-write
P12
Peripheral Select
12
1
read-write
P13
Peripheral Select
13
1
read-write
P14
Peripheral Select
14
1
read-write
P15
Peripheral Select
15
1
read-write
P16
Peripheral Select
16
1
read-write
P17
Peripheral Select
17
1
read-write
P18
Peripheral Select
18
1
read-write
P19
Peripheral Select
19
1
read-write
P2
Peripheral Select
2
1
read-write
P20
Peripheral Select
20
1
read-write
P21
Peripheral Select
21
1
read-write
P22
Peripheral Select
22
1
read-write
P23
Peripheral Select
23
1
read-write
P24
Peripheral Select
24
1
read-write
P25
Peripheral Select
25
1
read-write
P26
Peripheral Select
26
1
read-write
P27
Peripheral Select
27
1
read-write
P28
Peripheral Select
28
1
read-write
P29
Peripheral Select
29
1
read-write
P3
Peripheral Select
3
1
read-write
P30
Peripheral Select
30
1
read-write
P31
Peripheral Select
31
1
read-write
P4
Peripheral Select
4
1
read-write
P5
Peripheral Select
5
1
read-write
P6
Peripheral Select
6
1
read-write
P7
Peripheral Select
7
1
read-write
P8
Peripheral Select
8
1
read-write
P9
Peripheral Select
9
1
read-write
ABCDSR1
Peripheral Select Register
0x74
32
read-write
n
P0
Peripheral Select
0
1
read-write
P1
Peripheral Select
1
1
read-write
P10
Peripheral Select
10
1
read-write
P11
Peripheral Select
11
1
read-write
P12
Peripheral Select
12
1
read-write
P13
Peripheral Select
13
1
read-write
P14
Peripheral Select
14
1
read-write
P15
Peripheral Select
15
1
read-write
P16
Peripheral Select
16
1
read-write
P17
Peripheral Select
17
1
read-write
P18
Peripheral Select
18
1
read-write
P19
Peripheral Select
19
1
read-write
P2
Peripheral Select
2
1
read-write
P20
Peripheral Select
20
1
read-write
P21
Peripheral Select
21
1
read-write
P22
Peripheral Select
22
1
read-write
P23
Peripheral Select
23
1
read-write
P24
Peripheral Select
24
1
read-write
P25
Peripheral Select
25
1
read-write
P26
Peripheral Select
26
1
read-write
P27
Peripheral Select
27
1
read-write
P28
Peripheral Select
28
1
read-write
P29
Peripheral Select
29
1
read-write
P3
Peripheral Select
3
1
read-write
P30
Peripheral Select
30
1
read-write
P31
Peripheral Select
31
1
read-write
P4
Peripheral Select
4
1
read-write
P5
Peripheral Select
5
1
read-write
P6
Peripheral Select
6
1
read-write
P7
Peripheral Select
7
1
read-write
P8
Peripheral Select
8
1
read-write
P9
Peripheral Select
9
1
read-write
ABCDSR[0]
Peripheral Select Register
0xE0
32
read-write
n
0x0
0x0
P0
Peripheral Select
0
1
read-write
P1
Peripheral Select
1
1
read-write
P10
Peripheral Select
10
1
read-write
P11
Peripheral Select
11
1
read-write
P12
Peripheral Select
12
1
read-write
P13
Peripheral Select
13
1
read-write
P14
Peripheral Select
14
1
read-write
P15
Peripheral Select
15
1
read-write
P16
Peripheral Select
16
1
read-write
P17
Peripheral Select
17
1
read-write
P18
Peripheral Select
18
1
read-write
P19
Peripheral Select
19
1
read-write
P2
Peripheral Select
2
1
read-write
P20
Peripheral Select
20
1
read-write
P21
Peripheral Select
21
1
read-write
P22
Peripheral Select
22
1
read-write
P23
Peripheral Select
23
1
read-write
P24
Peripheral Select
24
1
read-write
P25
Peripheral Select
25
1
read-write
P26
Peripheral Select
26
1
read-write
P27
Peripheral Select
27
1
read-write
P28
Peripheral Select
28
1
read-write
P29
Peripheral Select
29
1
read-write
P3
Peripheral Select
3
1
read-write
P30
Peripheral Select
30
1
read-write
P31
Peripheral Select
31
1
read-write
P4
Peripheral Select
4
1
read-write
P5
Peripheral Select
5
1
read-write
P6
Peripheral Select
6
1
read-write
P7
Peripheral Select
7
1
read-write
P8
Peripheral Select
8
1
read-write
P9
Peripheral Select
9
1
read-write
ABCDSR[1]
Peripheral Select Register
0x154
32
read-write
n
0x0
0x0
P0
Peripheral Select
0
1
read-write
P1
Peripheral Select
1
1
read-write
P10
Peripheral Select
10
1
read-write
P11
Peripheral Select
11
1
read-write
P12
Peripheral Select
12
1
read-write
P13
Peripheral Select
13
1
read-write
P14
Peripheral Select
14
1
read-write
P15
Peripheral Select
15
1
read-write
P16
Peripheral Select
16
1
read-write
P17
Peripheral Select
17
1
read-write
P18
Peripheral Select
18
1
read-write
P19
Peripheral Select
19
1
read-write
P2
Peripheral Select
2
1
read-write
P20
Peripheral Select
20
1
read-write
P21
Peripheral Select
21
1
read-write
P22
Peripheral Select
22
1
read-write
P23
Peripheral Select
23
1
read-write
P24
Peripheral Select
24
1
read-write
P25
Peripheral Select
25
1
read-write
P26
Peripheral Select
26
1
read-write
P27
Peripheral Select
27
1
read-write
P28
Peripheral Select
28
1
read-write
P29
Peripheral Select
29
1
read-write
P3
Peripheral Select
3
1
read-write
P30
Peripheral Select
30
1
read-write
P31
Peripheral Select
31
1
read-write
P4
Peripheral Select
4
1
read-write
P5
Peripheral Select
5
1
read-write
P6
Peripheral Select
6
1
read-write
P7
Peripheral Select
7
1
read-write
P8
Peripheral Select
8
1
read-write
P9
Peripheral Select
9
1
read-write
AIMDR
Additional Interrupt Modes Disable Register
0xB4
32
write-only
n
0x0
0x0
P0
Additional Interrupt Modes Disable
0
1
write-only
P1
Additional Interrupt Modes Disable
1
1
write-only
P10
Additional Interrupt Modes Disable
10
1
write-only
P11
Additional Interrupt Modes Disable
11
1
write-only
P12
Additional Interrupt Modes Disable
12
1
write-only
P13
Additional Interrupt Modes Disable
13
1
write-only
P14
Additional Interrupt Modes Disable
14
1
write-only
P15
Additional Interrupt Modes Disable
15
1
write-only
P16
Additional Interrupt Modes Disable
16
1
write-only
P17
Additional Interrupt Modes Disable
17
1
write-only
P18
Additional Interrupt Modes Disable
18
1
write-only
P19
Additional Interrupt Modes Disable
19
1
write-only
P2
Additional Interrupt Modes Disable
2
1
write-only
P20
Additional Interrupt Modes Disable
20
1
write-only
P21
Additional Interrupt Modes Disable
21
1
write-only
P22
Additional Interrupt Modes Disable
22
1
write-only
P23
Additional Interrupt Modes Disable
23
1
write-only
P24
Additional Interrupt Modes Disable
24
1
write-only
P25
Additional Interrupt Modes Disable
25
1
write-only
P26
Additional Interrupt Modes Disable
26
1
write-only
P27
Additional Interrupt Modes Disable
27
1
write-only
P28
Additional Interrupt Modes Disable
28
1
write-only
P29
Additional Interrupt Modes Disable
29
1
write-only
P3
Additional Interrupt Modes Disable
3
1
write-only
P30
Additional Interrupt Modes Disable
30
1
write-only
P31
Additional Interrupt Modes Disable
31
1
write-only
P4
Additional Interrupt Modes Disable
4
1
write-only
P5
Additional Interrupt Modes Disable
5
1
write-only
P6
Additional Interrupt Modes Disable
6
1
write-only
P7
Additional Interrupt Modes Disable
7
1
write-only
P8
Additional Interrupt Modes Disable
8
1
write-only
P9
Additional Interrupt Modes Disable
9
1
write-only
AIMER
Additional Interrupt Modes Enable Register
0xB0
32
write-only
n
0x0
0x0
P0
Additional Interrupt Modes Enable
0
1
write-only
P1
Additional Interrupt Modes Enable
1
1
write-only
P10
Additional Interrupt Modes Enable
10
1
write-only
P11
Additional Interrupt Modes Enable
11
1
write-only
P12
Additional Interrupt Modes Enable
12
1
write-only
P13
Additional Interrupt Modes Enable
13
1
write-only
P14
Additional Interrupt Modes Enable
14
1
write-only
P15
Additional Interrupt Modes Enable
15
1
write-only
P16
Additional Interrupt Modes Enable
16
1
write-only
P17
Additional Interrupt Modes Enable
17
1
write-only
P18
Additional Interrupt Modes Enable
18
1
write-only
P19
Additional Interrupt Modes Enable
19
1
write-only
P2
Additional Interrupt Modes Enable
2
1
write-only
P20
Additional Interrupt Modes Enable
20
1
write-only
P21
Additional Interrupt Modes Enable
21
1
write-only
P22
Additional Interrupt Modes Enable
22
1
write-only
P23
Additional Interrupt Modes Enable
23
1
write-only
P24
Additional Interrupt Modes Enable
24
1
write-only
P25
Additional Interrupt Modes Enable
25
1
write-only
P26
Additional Interrupt Modes Enable
26
1
write-only
P27
Additional Interrupt Modes Enable
27
1
write-only
P28
Additional Interrupt Modes Enable
28
1
write-only
P29
Additional Interrupt Modes Enable
29
1
write-only
P3
Additional Interrupt Modes Enable
3
1
write-only
P30
Additional Interrupt Modes Enable
30
1
write-only
P31
Additional Interrupt Modes Enable
31
1
write-only
P4
Additional Interrupt Modes Enable
4
1
write-only
P5
Additional Interrupt Modes Enable
5
1
write-only
P6
Additional Interrupt Modes Enable
6
1
write-only
P7
Additional Interrupt Modes Enable
7
1
write-only
P8
Additional Interrupt Modes Enable
8
1
write-only
P9
Additional Interrupt Modes Enable
9
1
write-only
AIMMR
Additional Interrupt Modes Mask Register
0xB8
32
read-only
n
0x0
0x0
P0
IO Line Index
0
1
read-only
P1
IO Line Index
1
1
read-only
P10
IO Line Index
10
1
read-only
P11
IO Line Index
11
1
read-only
P12
IO Line Index
12
1
read-only
P13
IO Line Index
13
1
read-only
P14
IO Line Index
14
1
read-only
P15
IO Line Index
15
1
read-only
P16
IO Line Index
16
1
read-only
P17
IO Line Index
17
1
read-only
P18
IO Line Index
18
1
read-only
P19
IO Line Index
19
1
read-only
P2
IO Line Index
2
1
read-only
P20
IO Line Index
20
1
read-only
P21
IO Line Index
21
1
read-only
P22
IO Line Index
22
1
read-only
P23
IO Line Index
23
1
read-only
P24
IO Line Index
24
1
read-only
P25
IO Line Index
25
1
read-only
P26
IO Line Index
26
1
read-only
P27
IO Line Index
27
1
read-only
P28
IO Line Index
28
1
read-only
P29
IO Line Index
29
1
read-only
P3
IO Line Index
3
1
read-only
P30
IO Line Index
30
1
read-only
P31
IO Line Index
31
1
read-only
P4
IO Line Index
4
1
read-only
P5
IO Line Index
5
1
read-only
P6
IO Line Index
6
1
read-only
P7
IO Line Index
7
1
read-only
P8
IO Line Index
8
1
read-only
P9
IO Line Index
9
1
read-only
CODR
Clear Output Data Register
0x34
32
write-only
n
0x0
0x0
P0
Clear Output Data
0
1
write-only
P1
Clear Output Data
1
1
write-only
P10
Clear Output Data
10
1
write-only
P11
Clear Output Data
11
1
write-only
P12
Clear Output Data
12
1
write-only
P13
Clear Output Data
13
1
write-only
P14
Clear Output Data
14
1
write-only
P15
Clear Output Data
15
1
write-only
P16
Clear Output Data
16
1
write-only
P17
Clear Output Data
17
1
write-only
P18
Clear Output Data
18
1
write-only
P19
Clear Output Data
19
1
write-only
P2
Clear Output Data
2
1
write-only
P20
Clear Output Data
20
1
write-only
P21
Clear Output Data
21
1
write-only
P22
Clear Output Data
22
1
write-only
P23
Clear Output Data
23
1
write-only
P24
Clear Output Data
24
1
write-only
P25
Clear Output Data
25
1
write-only
P26
Clear Output Data
26
1
write-only
P27
Clear Output Data
27
1
write-only
P28
Clear Output Data
28
1
write-only
P29
Clear Output Data
29
1
write-only
P3
Clear Output Data
3
1
write-only
P30
Clear Output Data
30
1
write-only
P31
Clear Output Data
31
1
write-only
P4
Clear Output Data
4
1
write-only
P5
Clear Output Data
5
1
write-only
P6
Clear Output Data
6
1
write-only
P7
Clear Output Data
7
1
write-only
P8
Clear Output Data
8
1
write-only
P9
Clear Output Data
9
1
write-only
DRIVER
I/O Drive Register
0x118
32
read-write
n
0x0
0x0
LINE0
Drive of PIO Line 0
0
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE1
Drive of PIO Line 1
1
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE10
Drive of PIO Line 10
10
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE11
Drive of PIO Line 11
11
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE12
Drive of PIO Line 12
12
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE13
Drive of PIO Line 13
13
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE14
Drive of PIO Line 14
14
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE15
Drive of PIO Line 15
15
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE16
Drive of PIO Line 16
16
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE17
Drive of PIO Line 17
17
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE18
Drive of PIO Line 18
18
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE19
Drive of PIO Line 19
19
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE2
Drive of PIO Line 2
2
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE20
Drive of PIO Line 20
20
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE21
Drive of PIO Line 21
21
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE22
Drive of PIO Line 22
22
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE23
Drive of PIO Line 23
23
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE24
Drive of PIO Line 24
24
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE25
Drive of PIO Line 25
25
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE26
Drive of PIO Line 26
26
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE27
Drive of PIO Line 27
27
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE28
Drive of PIO Line 28
28
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE29
Drive of PIO Line 29
29
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE3
Drive of PIO Line 3
3
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE30
Drive of PIO Line 30
30
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE31
Drive of PIO Line 31
31
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE4
Drive of PIO Line 4
4
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE5
Drive of PIO Line 5
5
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE6
Drive of PIO Line 6
6
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE7
Drive of PIO Line 7
7
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE8
Drive of PIO Line 8
8
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE9
Drive of PIO Line 9
9
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
ELSR
Edge/Level Status Register
0xC8
32
read-only
n
0x0
0x0
P0
Edge/Level Interrupt Source Selection
0
1
read-only
P1
Edge/Level Interrupt Source Selection
1
1
read-only
P10
Edge/Level Interrupt Source Selection
10
1
read-only
P11
Edge/Level Interrupt Source Selection
11
1
read-only
P12
Edge/Level Interrupt Source Selection
12
1
read-only
P13
Edge/Level Interrupt Source Selection
13
1
read-only
P14
Edge/Level Interrupt Source Selection
14
1
read-only
P15
Edge/Level Interrupt Source Selection
15
1
read-only
P16
Edge/Level Interrupt Source Selection
16
1
read-only
P17
Edge/Level Interrupt Source Selection
17
1
read-only
P18
Edge/Level Interrupt Source Selection
18
1
read-only
P19
Edge/Level Interrupt Source Selection
19
1
read-only
P2
Edge/Level Interrupt Source Selection
2
1
read-only
P20
Edge/Level Interrupt Source Selection
20
1
read-only
P21
Edge/Level Interrupt Source Selection
21
1
read-only
P22
Edge/Level Interrupt Source Selection
22
1
read-only
P23
Edge/Level Interrupt Source Selection
23
1
read-only
P24
Edge/Level Interrupt Source Selection
24
1
read-only
P25
Edge/Level Interrupt Source Selection
25
1
read-only
P26
Edge/Level Interrupt Source Selection
26
1
read-only
P27
Edge/Level Interrupt Source Selection
27
1
read-only
P28
Edge/Level Interrupt Source Selection
28
1
read-only
P29
Edge/Level Interrupt Source Selection
29
1
read-only
P3
Edge/Level Interrupt Source Selection
3
1
read-only
P30
Edge/Level Interrupt Source Selection
30
1
read-only
P31
Edge/Level Interrupt Source Selection
31
1
read-only
P4
Edge/Level Interrupt Source Selection
4
1
read-only
P5
Edge/Level Interrupt Source Selection
5
1
read-only
P6
Edge/Level Interrupt Source Selection
6
1
read-only
P7
Edge/Level Interrupt Source Selection
7
1
read-only
P8
Edge/Level Interrupt Source Selection
8
1
read-only
P9
Edge/Level Interrupt Source Selection
9
1
read-only
ESR
Edge Select Register
0xC0
32
write-only
n
0x0
0x0
P0
Edge Interrupt Selection
0
1
write-only
P1
Edge Interrupt Selection
1
1
write-only
P10
Edge Interrupt Selection
10
1
write-only
P11
Edge Interrupt Selection
11
1
write-only
P12
Edge Interrupt Selection
12
1
write-only
P13
Edge Interrupt Selection
13
1
write-only
P14
Edge Interrupt Selection
14
1
write-only
P15
Edge Interrupt Selection
15
1
write-only
P16
Edge Interrupt Selection
16
1
write-only
P17
Edge Interrupt Selection
17
1
write-only
P18
Edge Interrupt Selection
18
1
write-only
P19
Edge Interrupt Selection
19
1
write-only
P2
Edge Interrupt Selection
2
1
write-only
P20
Edge Interrupt Selection
20
1
write-only
P21
Edge Interrupt Selection
21
1
write-only
P22
Edge Interrupt Selection
22
1
write-only
P23
Edge Interrupt Selection
23
1
write-only
P24
Edge Interrupt Selection
24
1
write-only
P25
Edge Interrupt Selection
25
1
write-only
P26
Edge Interrupt Selection
26
1
write-only
P27
Edge Interrupt Selection
27
1
write-only
P28
Edge Interrupt Selection
28
1
write-only
P29
Edge Interrupt Selection
29
1
write-only
P3
Edge Interrupt Selection
3
1
write-only
P30
Edge Interrupt Selection
30
1
write-only
P31
Edge Interrupt Selection
31
1
write-only
P4
Edge Interrupt Selection
4
1
write-only
P5
Edge Interrupt Selection
5
1
write-only
P6
Edge Interrupt Selection
6
1
write-only
P7
Edge Interrupt Selection
7
1
write-only
P8
Edge Interrupt Selection
8
1
write-only
P9
Edge Interrupt Selection
9
1
write-only
FELLSR
Falling Edge/Low-Level Select Register
0xD0
32
write-only
n
0x0
0x0
P0
Falling Edge/Low-Level Interrupt Selection
0
1
write-only
P1
Falling Edge/Low-Level Interrupt Selection
1
1
write-only
P10
Falling Edge/Low-Level Interrupt Selection
10
1
write-only
P11
Falling Edge/Low-Level Interrupt Selection
11
1
write-only
P12
Falling Edge/Low-Level Interrupt Selection
12
1
write-only
P13
Falling Edge/Low-Level Interrupt Selection
13
1
write-only
P14
Falling Edge/Low-Level Interrupt Selection
14
1
write-only
P15
Falling Edge/Low-Level Interrupt Selection
15
1
write-only
P16
Falling Edge/Low-Level Interrupt Selection
16
1
write-only
P17
Falling Edge/Low-Level Interrupt Selection
17
1
write-only
P18
Falling Edge/Low-Level Interrupt Selection
18
1
write-only
P19
Falling Edge/Low-Level Interrupt Selection
19
1
write-only
P2
Falling Edge/Low-Level Interrupt Selection
2
1
write-only
P20
Falling Edge/Low-Level Interrupt Selection
20
1
write-only
P21
Falling Edge/Low-Level Interrupt Selection
21
1
write-only
P22
Falling Edge/Low-Level Interrupt Selection
22
1
write-only
P23
Falling Edge/Low-Level Interrupt Selection
23
1
write-only
P24
Falling Edge/Low-Level Interrupt Selection
24
1
write-only
P25
Falling Edge/Low-Level Interrupt Selection
25
1
write-only
P26
Falling Edge/Low-Level Interrupt Selection
26
1
write-only
P27
Falling Edge/Low-Level Interrupt Selection
27
1
write-only
P28
Falling Edge/Low-Level Interrupt Selection
28
1
write-only
P29
Falling Edge/Low-Level Interrupt Selection
29
1
write-only
P3
Falling Edge/Low-Level Interrupt Selection
3
1
write-only
P30
Falling Edge/Low-Level Interrupt Selection
30
1
write-only
P31
Falling Edge/Low-Level Interrupt Selection
31
1
write-only
P4
Falling Edge/Low-Level Interrupt Selection
4
1
write-only
P5
Falling Edge/Low-Level Interrupt Selection
5
1
write-only
P6
Falling Edge/Low-Level Interrupt Selection
6
1
write-only
P7
Falling Edge/Low-Level Interrupt Selection
7
1
write-only
P8
Falling Edge/Low-Level Interrupt Selection
8
1
write-only
P9
Falling Edge/Low-Level Interrupt Selection
9
1
write-only
FRLHSR
Fall/Rise - Low/High Status Register
0xD8
32
read-only
n
0x0
0x0
P0
Edge/Level Interrupt Source Selection
0
1
read-only
P1
Edge/Level Interrupt Source Selection
1
1
read-only
P10
Edge/Level Interrupt Source Selection
10
1
read-only
P11
Edge/Level Interrupt Source Selection
11
1
read-only
P12
Edge/Level Interrupt Source Selection
12
1
read-only
P13
Edge/Level Interrupt Source Selection
13
1
read-only
P14
Edge/Level Interrupt Source Selection
14
1
read-only
P15
Edge/Level Interrupt Source Selection
15
1
read-only
P16
Edge/Level Interrupt Source Selection
16
1
read-only
P17
Edge/Level Interrupt Source Selection
17
1
read-only
P18
Edge/Level Interrupt Source Selection
18
1
read-only
P19
Edge/Level Interrupt Source Selection
19
1
read-only
P2
Edge/Level Interrupt Source Selection
2
1
read-only
P20
Edge/Level Interrupt Source Selection
20
1
read-only
P21
Edge/Level Interrupt Source Selection
21
1
read-only
P22
Edge/Level Interrupt Source Selection
22
1
read-only
P23
Edge/Level Interrupt Source Selection
23
1
read-only
P24
Edge/Level Interrupt Source Selection
24
1
read-only
P25
Edge/Level Interrupt Source Selection
25
1
read-only
P26
Edge/Level Interrupt Source Selection
26
1
read-only
P27
Edge/Level Interrupt Source Selection
27
1
read-only
P28
Edge/Level Interrupt Source Selection
28
1
read-only
P29
Edge/Level Interrupt Source Selection
29
1
read-only
P3
Edge/Level Interrupt Source Selection
3
1
read-only
P30
Edge/Level Interrupt Source Selection
30
1
read-only
P31
Edge/Level Interrupt Source Selection
31
1
read-only
P4
Edge/Level Interrupt Source Selection
4
1
read-only
P5
Edge/Level Interrupt Source Selection
5
1
read-only
P6
Edge/Level Interrupt Source Selection
6
1
read-only
P7
Edge/Level Interrupt Source Selection
7
1
read-only
P8
Edge/Level Interrupt Source Selection
8
1
read-only
P9
Edge/Level Interrupt Source Selection
9
1
read-only
IDR
Interrupt Disable Register
0x44
32
write-only
n
0x0
0x0
P0
Input Change Interrupt Disable
0
1
write-only
P1
Input Change Interrupt Disable
1
1
write-only
P10
Input Change Interrupt Disable
10
1
write-only
P11
Input Change Interrupt Disable
11
1
write-only
P12
Input Change Interrupt Disable
12
1
write-only
P13
Input Change Interrupt Disable
13
1
write-only
P14
Input Change Interrupt Disable
14
1
write-only
P15
Input Change Interrupt Disable
15
1
write-only
P16
Input Change Interrupt Disable
16
1
write-only
P17
Input Change Interrupt Disable
17
1
write-only
P18
Input Change Interrupt Disable
18
1
write-only
P19
Input Change Interrupt Disable
19
1
write-only
P2
Input Change Interrupt Disable
2
1
write-only
P20
Input Change Interrupt Disable
20
1
write-only
P21
Input Change Interrupt Disable
21
1
write-only
P22
Input Change Interrupt Disable
22
1
write-only
P23
Input Change Interrupt Disable
23
1
write-only
P24
Input Change Interrupt Disable
24
1
write-only
P25
Input Change Interrupt Disable
25
1
write-only
P26
Input Change Interrupt Disable
26
1
write-only
P27
Input Change Interrupt Disable
27
1
write-only
P28
Input Change Interrupt Disable
28
1
write-only
P29
Input Change Interrupt Disable
29
1
write-only
P3
Input Change Interrupt Disable
3
1
write-only
P30
Input Change Interrupt Disable
30
1
write-only
P31
Input Change Interrupt Disable
31
1
write-only
P4
Input Change Interrupt Disable
4
1
write-only
P5
Input Change Interrupt Disable
5
1
write-only
P6
Input Change Interrupt Disable
6
1
write-only
P7
Input Change Interrupt Disable
7
1
write-only
P8
Input Change Interrupt Disable
8
1
write-only
P9
Input Change Interrupt Disable
9
1
write-only
IER
Interrupt Enable Register
0x40
32
write-only
n
0x0
0x0
P0
Input Change Interrupt Enable
0
1
write-only
P1
Input Change Interrupt Enable
1
1
write-only
P10
Input Change Interrupt Enable
10
1
write-only
P11
Input Change Interrupt Enable
11
1
write-only
P12
Input Change Interrupt Enable
12
1
write-only
P13
Input Change Interrupt Enable
13
1
write-only
P14
Input Change Interrupt Enable
14
1
write-only
P15
Input Change Interrupt Enable
15
1
write-only
P16
Input Change Interrupt Enable
16
1
write-only
P17
Input Change Interrupt Enable
17
1
write-only
P18
Input Change Interrupt Enable
18
1
write-only
P19
Input Change Interrupt Enable
19
1
write-only
P2
Input Change Interrupt Enable
2
1
write-only
P20
Input Change Interrupt Enable
20
1
write-only
P21
Input Change Interrupt Enable
21
1
write-only
P22
Input Change Interrupt Enable
22
1
write-only
P23
Input Change Interrupt Enable
23
1
write-only
P24
Input Change Interrupt Enable
24
1
write-only
P25
Input Change Interrupt Enable
25
1
write-only
P26
Input Change Interrupt Enable
26
1
write-only
P27
Input Change Interrupt Enable
27
1
write-only
P28
Input Change Interrupt Enable
28
1
write-only
P29
Input Change Interrupt Enable
29
1
write-only
P3
Input Change Interrupt Enable
3
1
write-only
P30
Input Change Interrupt Enable
30
1
write-only
P31
Input Change Interrupt Enable
31
1
write-only
P4
Input Change Interrupt Enable
4
1
write-only
P5
Input Change Interrupt Enable
5
1
write-only
P6
Input Change Interrupt Enable
6
1
write-only
P7
Input Change Interrupt Enable
7
1
write-only
P8
Input Change Interrupt Enable
8
1
write-only
P9
Input Change Interrupt Enable
9
1
write-only
IFDR
Glitch Input Filter Disable Register
0x24
32
write-only
n
0x0
0x0
P0
Input Filter Disable
0
1
write-only
P1
Input Filter Disable
1
1
write-only
P10
Input Filter Disable
10
1
write-only
P11
Input Filter Disable
11
1
write-only
P12
Input Filter Disable
12
1
write-only
P13
Input Filter Disable
13
1
write-only
P14
Input Filter Disable
14
1
write-only
P15
Input Filter Disable
15
1
write-only
P16
Input Filter Disable
16
1
write-only
P17
Input Filter Disable
17
1
write-only
P18
Input Filter Disable
18
1
write-only
P19
Input Filter Disable
19
1
write-only
P2
Input Filter Disable
2
1
write-only
P20
Input Filter Disable
20
1
write-only
P21
Input Filter Disable
21
1
write-only
P22
Input Filter Disable
22
1
write-only
P23
Input Filter Disable
23
1
write-only
P24
Input Filter Disable
24
1
write-only
P25
Input Filter Disable
25
1
write-only
P26
Input Filter Disable
26
1
write-only
P27
Input Filter Disable
27
1
write-only
P28
Input Filter Disable
28
1
write-only
P29
Input Filter Disable
29
1
write-only
P3
Input Filter Disable
3
1
write-only
P30
Input Filter Disable
30
1
write-only
P31
Input Filter Disable
31
1
write-only
P4
Input Filter Disable
4
1
write-only
P5
Input Filter Disable
5
1
write-only
P6
Input Filter Disable
6
1
write-only
P7
Input Filter Disable
7
1
write-only
P8
Input Filter Disable
8
1
write-only
P9
Input Filter Disable
9
1
write-only
IFER
Glitch Input Filter Enable Register
0x20
32
write-only
n
0x0
0x0
P0
Input Filter Enable
0
1
write-only
P1
Input Filter Enable
1
1
write-only
P10
Input Filter Enable
10
1
write-only
P11
Input Filter Enable
11
1
write-only
P12
Input Filter Enable
12
1
write-only
P13
Input Filter Enable
13
1
write-only
P14
Input Filter Enable
14
1
write-only
P15
Input Filter Enable
15
1
write-only
P16
Input Filter Enable
16
1
write-only
P17
Input Filter Enable
17
1
write-only
P18
Input Filter Enable
18
1
write-only
P19
Input Filter Enable
19
1
write-only
P2
Input Filter Enable
2
1
write-only
P20
Input Filter Enable
20
1
write-only
P21
Input Filter Enable
21
1
write-only
P22
Input Filter Enable
22
1
write-only
P23
Input Filter Enable
23
1
write-only
P24
Input Filter Enable
24
1
write-only
P25
Input Filter Enable
25
1
write-only
P26
Input Filter Enable
26
1
write-only
P27
Input Filter Enable
27
1
write-only
P28
Input Filter Enable
28
1
write-only
P29
Input Filter Enable
29
1
write-only
P3
Input Filter Enable
3
1
write-only
P30
Input Filter Enable
30
1
write-only
P31
Input Filter Enable
31
1
write-only
P4
Input Filter Enable
4
1
write-only
P5
Input Filter Enable
5
1
write-only
P6
Input Filter Enable
6
1
write-only
P7
Input Filter Enable
7
1
write-only
P8
Input Filter Enable
8
1
write-only
P9
Input Filter Enable
9
1
write-only
IFSCDR
Input Filter Slow Clock Disable Register
0x80
32
write-only
n
0x0
0x0
P0
Peripheral Clock Glitch Filtering Select
0
1
write-only
P1
Peripheral Clock Glitch Filtering Select
1
1
write-only
P10
Peripheral Clock Glitch Filtering Select
10
1
write-only
P11
Peripheral Clock Glitch Filtering Select
11
1
write-only
P12
Peripheral Clock Glitch Filtering Select
12
1
write-only
P13
Peripheral Clock Glitch Filtering Select
13
1
write-only
P14
Peripheral Clock Glitch Filtering Select
14
1
write-only
P15
Peripheral Clock Glitch Filtering Select
15
1
write-only
P16
Peripheral Clock Glitch Filtering Select
16
1
write-only
P17
Peripheral Clock Glitch Filtering Select
17
1
write-only
P18
Peripheral Clock Glitch Filtering Select
18
1
write-only
P19
Peripheral Clock Glitch Filtering Select
19
1
write-only
P2
Peripheral Clock Glitch Filtering Select
2
1
write-only
P20
Peripheral Clock Glitch Filtering Select
20
1
write-only
P21
Peripheral Clock Glitch Filtering Select
21
1
write-only
P22
Peripheral Clock Glitch Filtering Select
22
1
write-only
P23
Peripheral Clock Glitch Filtering Select
23
1
write-only
P24
Peripheral Clock Glitch Filtering Select
24
1
write-only
P25
Peripheral Clock Glitch Filtering Select
25
1
write-only
P26
Peripheral Clock Glitch Filtering Select
26
1
write-only
P27
Peripheral Clock Glitch Filtering Select
27
1
write-only
P28
Peripheral Clock Glitch Filtering Select
28
1
write-only
P29
Peripheral Clock Glitch Filtering Select
29
1
write-only
P3
Peripheral Clock Glitch Filtering Select
3
1
write-only
P30
Peripheral Clock Glitch Filtering Select
30
1
write-only
P31
Peripheral Clock Glitch Filtering Select
31
1
write-only
P4
Peripheral Clock Glitch Filtering Select
4
1
write-only
P5
Peripheral Clock Glitch Filtering Select
5
1
write-only
P6
Peripheral Clock Glitch Filtering Select
6
1
write-only
P7
Peripheral Clock Glitch Filtering Select
7
1
write-only
P8
Peripheral Clock Glitch Filtering Select
8
1
write-only
P9
Peripheral Clock Glitch Filtering Select
9
1
write-only
IFSCER
Input Filter Slow Clock Enable Register
0x84
32
write-only
n
0x0
0x0
P0
Slow Clock Debouncing Filtering Select
0
1
write-only
P1
Slow Clock Debouncing Filtering Select
1
1
write-only
P10
Slow Clock Debouncing Filtering Select
10
1
write-only
P11
Slow Clock Debouncing Filtering Select
11
1
write-only
P12
Slow Clock Debouncing Filtering Select
12
1
write-only
P13
Slow Clock Debouncing Filtering Select
13
1
write-only
P14
Slow Clock Debouncing Filtering Select
14
1
write-only
P15
Slow Clock Debouncing Filtering Select
15
1
write-only
P16
Slow Clock Debouncing Filtering Select
16
1
write-only
P17
Slow Clock Debouncing Filtering Select
17
1
write-only
P18
Slow Clock Debouncing Filtering Select
18
1
write-only
P19
Slow Clock Debouncing Filtering Select
19
1
write-only
P2
Slow Clock Debouncing Filtering Select
2
1
write-only
P20
Slow Clock Debouncing Filtering Select
20
1
write-only
P21
Slow Clock Debouncing Filtering Select
21
1
write-only
P22
Slow Clock Debouncing Filtering Select
22
1
write-only
P23
Slow Clock Debouncing Filtering Select
23
1
write-only
P24
Slow Clock Debouncing Filtering Select
24
1
write-only
P25
Slow Clock Debouncing Filtering Select
25
1
write-only
P26
Slow Clock Debouncing Filtering Select
26
1
write-only
P27
Slow Clock Debouncing Filtering Select
27
1
write-only
P28
Slow Clock Debouncing Filtering Select
28
1
write-only
P29
Slow Clock Debouncing Filtering Select
29
1
write-only
P3
Slow Clock Debouncing Filtering Select
3
1
write-only
P30
Slow Clock Debouncing Filtering Select
30
1
write-only
P31
Slow Clock Debouncing Filtering Select
31
1
write-only
P4
Slow Clock Debouncing Filtering Select
4
1
write-only
P5
Slow Clock Debouncing Filtering Select
5
1
write-only
P6
Slow Clock Debouncing Filtering Select
6
1
write-only
P7
Slow Clock Debouncing Filtering Select
7
1
write-only
P8
Slow Clock Debouncing Filtering Select
8
1
write-only
P9
Slow Clock Debouncing Filtering Select
9
1
write-only
IFSCSR
Input Filter Slow Clock Status Register
0x88
32
read-only
n
0x0
0x0
P0
Glitch or Debouncing Filter Selection Status
0
1
read-only
P1
Glitch or Debouncing Filter Selection Status
1
1
read-only
P10
Glitch or Debouncing Filter Selection Status
10
1
read-only
P11
Glitch or Debouncing Filter Selection Status
11
1
read-only
P12
Glitch or Debouncing Filter Selection Status
12
1
read-only
P13
Glitch or Debouncing Filter Selection Status
13
1
read-only
P14
Glitch or Debouncing Filter Selection Status
14
1
read-only
P15
Glitch or Debouncing Filter Selection Status
15
1
read-only
P16
Glitch or Debouncing Filter Selection Status
16
1
read-only
P17
Glitch or Debouncing Filter Selection Status
17
1
read-only
P18
Glitch or Debouncing Filter Selection Status
18
1
read-only
P19
Glitch or Debouncing Filter Selection Status
19
1
read-only
P2
Glitch or Debouncing Filter Selection Status
2
1
read-only
P20
Glitch or Debouncing Filter Selection Status
20
1
read-only
P21
Glitch or Debouncing Filter Selection Status
21
1
read-only
P22
Glitch or Debouncing Filter Selection Status
22
1
read-only
P23
Glitch or Debouncing Filter Selection Status
23
1
read-only
P24
Glitch or Debouncing Filter Selection Status
24
1
read-only
P25
Glitch or Debouncing Filter Selection Status
25
1
read-only
P26
Glitch or Debouncing Filter Selection Status
26
1
read-only
P27
Glitch or Debouncing Filter Selection Status
27
1
read-only
P28
Glitch or Debouncing Filter Selection Status
28
1
read-only
P29
Glitch or Debouncing Filter Selection Status
29
1
read-only
P3
Glitch or Debouncing Filter Selection Status
3
1
read-only
P30
Glitch or Debouncing Filter Selection Status
30
1
read-only
P31
Glitch or Debouncing Filter Selection Status
31
1
read-only
P4
Glitch or Debouncing Filter Selection Status
4
1
read-only
P5
Glitch or Debouncing Filter Selection Status
5
1
read-only
P6
Glitch or Debouncing Filter Selection Status
6
1
read-only
P7
Glitch or Debouncing Filter Selection Status
7
1
read-only
P8
Glitch or Debouncing Filter Selection Status
8
1
read-only
P9
Glitch or Debouncing Filter Selection Status
9
1
read-only
IFSR
Glitch Input Filter Status Register
0x28
32
read-only
n
0x0
0x0
P0
Input Filer Status
0
1
read-only
P1
Input Filer Status
1
1
read-only
P10
Input Filer Status
10
1
read-only
P11
Input Filer Status
11
1
read-only
P12
Input Filer Status
12
1
read-only
P13
Input Filer Status
13
1
read-only
P14
Input Filer Status
14
1
read-only
P15
Input Filer Status
15
1
read-only
P16
Input Filer Status
16
1
read-only
P17
Input Filer Status
17
1
read-only
P18
Input Filer Status
18
1
read-only
P19
Input Filer Status
19
1
read-only
P2
Input Filer Status
2
1
read-only
P20
Input Filer Status
20
1
read-only
P21
Input Filer Status
21
1
read-only
P22
Input Filer Status
22
1
read-only
P23
Input Filer Status
23
1
read-only
P24
Input Filer Status
24
1
read-only
P25
Input Filer Status
25
1
read-only
P26
Input Filer Status
26
1
read-only
P27
Input Filer Status
27
1
read-only
P28
Input Filer Status
28
1
read-only
P29
Input Filer Status
29
1
read-only
P3
Input Filer Status
3
1
read-only
P30
Input Filer Status
30
1
read-only
P31
Input Filer Status
31
1
read-only
P4
Input Filer Status
4
1
read-only
P5
Input Filer Status
5
1
read-only
P6
Input Filer Status
6
1
read-only
P7
Input Filer Status
7
1
read-only
P8
Input Filer Status
8
1
read-only
P9
Input Filer Status
9
1
read-only
IMR
Interrupt Mask Register
0x48
32
read-only
n
0x0
0x0
P0
Input Change Interrupt Mask
0
1
read-only
P1
Input Change Interrupt Mask
1
1
read-only
P10
Input Change Interrupt Mask
10
1
read-only
P11
Input Change Interrupt Mask
11
1
read-only
P12
Input Change Interrupt Mask
12
1
read-only
P13
Input Change Interrupt Mask
13
1
read-only
P14
Input Change Interrupt Mask
14
1
read-only
P15
Input Change Interrupt Mask
15
1
read-only
P16
Input Change Interrupt Mask
16
1
read-only
P17
Input Change Interrupt Mask
17
1
read-only
P18
Input Change Interrupt Mask
18
1
read-only
P19
Input Change Interrupt Mask
19
1
read-only
P2
Input Change Interrupt Mask
2
1
read-only
P20
Input Change Interrupt Mask
20
1
read-only
P21
Input Change Interrupt Mask
21
1
read-only
P22
Input Change Interrupt Mask
22
1
read-only
P23
Input Change Interrupt Mask
23
1
read-only
P24
Input Change Interrupt Mask
24
1
read-only
P25
Input Change Interrupt Mask
25
1
read-only
P26
Input Change Interrupt Mask
26
1
read-only
P27
Input Change Interrupt Mask
27
1
read-only
P28
Input Change Interrupt Mask
28
1
read-only
P29
Input Change Interrupt Mask
29
1
read-only
P3
Input Change Interrupt Mask
3
1
read-only
P30
Input Change Interrupt Mask
30
1
read-only
P31
Input Change Interrupt Mask
31
1
read-only
P4
Input Change Interrupt Mask
4
1
read-only
P5
Input Change Interrupt Mask
5
1
read-only
P6
Input Change Interrupt Mask
6
1
read-only
P7
Input Change Interrupt Mask
7
1
read-only
P8
Input Change Interrupt Mask
8
1
read-only
P9
Input Change Interrupt Mask
9
1
read-only
ISR
Interrupt Status Register
0x4C
32
read-only
n
0x0
0x0
P0
Input Change Interrupt Status
0
1
read-only
P1
Input Change Interrupt Status
1
1
read-only
P10
Input Change Interrupt Status
10
1
read-only
P11
Input Change Interrupt Status
11
1
read-only
P12
Input Change Interrupt Status
12
1
read-only
P13
Input Change Interrupt Status
13
1
read-only
P14
Input Change Interrupt Status
14
1
read-only
P15
Input Change Interrupt Status
15
1
read-only
P16
Input Change Interrupt Status
16
1
read-only
P17
Input Change Interrupt Status
17
1
read-only
P18
Input Change Interrupt Status
18
1
read-only
P19
Input Change Interrupt Status
19
1
read-only
P2
Input Change Interrupt Status
2
1
read-only
P20
Input Change Interrupt Status
20
1
read-only
P21
Input Change Interrupt Status
21
1
read-only
P22
Input Change Interrupt Status
22
1
read-only
P23
Input Change Interrupt Status
23
1
read-only
P24
Input Change Interrupt Status
24
1
read-only
P25
Input Change Interrupt Status
25
1
read-only
P26
Input Change Interrupt Status
26
1
read-only
P27
Input Change Interrupt Status
27
1
read-only
P28
Input Change Interrupt Status
28
1
read-only
P29
Input Change Interrupt Status
29
1
read-only
P3
Input Change Interrupt Status
3
1
read-only
P30
Input Change Interrupt Status
30
1
read-only
P31
Input Change Interrupt Status
31
1
read-only
P4
Input Change Interrupt Status
4
1
read-only
P5
Input Change Interrupt Status
5
1
read-only
P6
Input Change Interrupt Status
6
1
read-only
P7
Input Change Interrupt Status
7
1
read-only
P8
Input Change Interrupt Status
8
1
read-only
P9
Input Change Interrupt Status
9
1
read-only
LSR
Level Select Register
0xC4
32
write-only
n
0x0
0x0
P0
Level Interrupt Selection
0
1
write-only
P1
Level Interrupt Selection
1
1
write-only
P10
Level Interrupt Selection
10
1
write-only
P11
Level Interrupt Selection
11
1
write-only
P12
Level Interrupt Selection
12
1
write-only
P13
Level Interrupt Selection
13
1
write-only
P14
Level Interrupt Selection
14
1
write-only
P15
Level Interrupt Selection
15
1
write-only
P16
Level Interrupt Selection
16
1
write-only
P17
Level Interrupt Selection
17
1
write-only
P18
Level Interrupt Selection
18
1
write-only
P19
Level Interrupt Selection
19
1
write-only
P2
Level Interrupt Selection
2
1
write-only
P20
Level Interrupt Selection
20
1
write-only
P21
Level Interrupt Selection
21
1
write-only
P22
Level Interrupt Selection
22
1
write-only
P23
Level Interrupt Selection
23
1
write-only
P24
Level Interrupt Selection
24
1
write-only
P25
Level Interrupt Selection
25
1
write-only
P26
Level Interrupt Selection
26
1
write-only
P27
Level Interrupt Selection
27
1
write-only
P28
Level Interrupt Selection
28
1
write-only
P29
Level Interrupt Selection
29
1
write-only
P3
Level Interrupt Selection
3
1
write-only
P30
Level Interrupt Selection
30
1
write-only
P31
Level Interrupt Selection
31
1
write-only
P4
Level Interrupt Selection
4
1
write-only
P5
Level Interrupt Selection
5
1
write-only
P6
Level Interrupt Selection
6
1
write-only
P7
Level Interrupt Selection
7
1
write-only
P8
Level Interrupt Selection
8
1
write-only
P9
Level Interrupt Selection
9
1
write-only
MDDR
Multi-driver Disable Register
0x54
32
write-only
n
0x0
0x0
P0
Multi-drive Disable
0
1
write-only
P1
Multi-drive Disable
1
1
write-only
P10
Multi-drive Disable
10
1
write-only
P11
Multi-drive Disable
11
1
write-only
P12
Multi-drive Disable
12
1
write-only
P13
Multi-drive Disable
13
1
write-only
P14
Multi-drive Disable
14
1
write-only
P15
Multi-drive Disable
15
1
write-only
P16
Multi-drive Disable
16
1
write-only
P17
Multi-drive Disable
17
1
write-only
P18
Multi-drive Disable
18
1
write-only
P19
Multi-drive Disable
19
1
write-only
P2
Multi-drive Disable
2
1
write-only
P20
Multi-drive Disable
20
1
write-only
P21
Multi-drive Disable
21
1
write-only
P22
Multi-drive Disable
22
1
write-only
P23
Multi-drive Disable
23
1
write-only
P24
Multi-drive Disable
24
1
write-only
P25
Multi-drive Disable
25
1
write-only
P26
Multi-drive Disable
26
1
write-only
P27
Multi-drive Disable
27
1
write-only
P28
Multi-drive Disable
28
1
write-only
P29
Multi-drive Disable
29
1
write-only
P3
Multi-drive Disable
3
1
write-only
P30
Multi-drive Disable
30
1
write-only
P31
Multi-drive Disable
31
1
write-only
P4
Multi-drive Disable
4
1
write-only
P5
Multi-drive Disable
5
1
write-only
P6
Multi-drive Disable
6
1
write-only
P7
Multi-drive Disable
7
1
write-only
P8
Multi-drive Disable
8
1
write-only
P9
Multi-drive Disable
9
1
write-only
MDER
Multi-driver Enable Register
0x50
32
write-only
n
0x0
0x0
P0
Multi-drive Enable
0
1
write-only
P1
Multi-drive Enable
1
1
write-only
P10
Multi-drive Enable
10
1
write-only
P11
Multi-drive Enable
11
1
write-only
P12
Multi-drive Enable
12
1
write-only
P13
Multi-drive Enable
13
1
write-only
P14
Multi-drive Enable
14
1
write-only
P15
Multi-drive Enable
15
1
write-only
P16
Multi-drive Enable
16
1
write-only
P17
Multi-drive Enable
17
1
write-only
P18
Multi-drive Enable
18
1
write-only
P19
Multi-drive Enable
19
1
write-only
P2
Multi-drive Enable
2
1
write-only
P20
Multi-drive Enable
20
1
write-only
P21
Multi-drive Enable
21
1
write-only
P22
Multi-drive Enable
22
1
write-only
P23
Multi-drive Enable
23
1
write-only
P24
Multi-drive Enable
24
1
write-only
P25
Multi-drive Enable
25
1
write-only
P26
Multi-drive Enable
26
1
write-only
P27
Multi-drive Enable
27
1
write-only
P28
Multi-drive Enable
28
1
write-only
P29
Multi-drive Enable
29
1
write-only
P3
Multi-drive Enable
3
1
write-only
P30
Multi-drive Enable
30
1
write-only
P31
Multi-drive Enable
31
1
write-only
P4
Multi-drive Enable
4
1
write-only
P5
Multi-drive Enable
5
1
write-only
P6
Multi-drive Enable
6
1
write-only
P7
Multi-drive Enable
7
1
write-only
P8
Multi-drive Enable
8
1
write-only
P9
Multi-drive Enable
9
1
write-only
MDSR
Multi-driver Status Register
0x58
32
read-only
n
0x0
0x0
P0
Multi-drive Status
0
1
read-only
P1
Multi-drive Status
1
1
read-only
P10
Multi-drive Status
10
1
read-only
P11
Multi-drive Status
11
1
read-only
P12
Multi-drive Status
12
1
read-only
P13
Multi-drive Status
13
1
read-only
P14
Multi-drive Status
14
1
read-only
P15
Multi-drive Status
15
1
read-only
P16
Multi-drive Status
16
1
read-only
P17
Multi-drive Status
17
1
read-only
P18
Multi-drive Status
18
1
read-only
P19
Multi-drive Status
19
1
read-only
P2
Multi-drive Status
2
1
read-only
P20
Multi-drive Status
20
1
read-only
P21
Multi-drive Status
21
1
read-only
P22
Multi-drive Status
22
1
read-only
P23
Multi-drive Status
23
1
read-only
P24
Multi-drive Status
24
1
read-only
P25
Multi-drive Status
25
1
read-only
P26
Multi-drive Status
26
1
read-only
P27
Multi-drive Status
27
1
read-only
P28
Multi-drive Status
28
1
read-only
P29
Multi-drive Status
29
1
read-only
P3
Multi-drive Status
3
1
read-only
P30
Multi-drive Status
30
1
read-only
P31
Multi-drive Status
31
1
read-only
P4
Multi-drive Status
4
1
read-only
P5
Multi-drive Status
5
1
read-only
P6
Multi-drive Status
6
1
read-only
P7
Multi-drive Status
7
1
read-only
P8
Multi-drive Status
8
1
read-only
P9
Multi-drive Status
9
1
read-only
ODR
Output Disable Register
0x14
32
write-only
n
0x0
0x0
P0
Output Disable
0
1
write-only
P1
Output Disable
1
1
write-only
P10
Output Disable
10
1
write-only
P11
Output Disable
11
1
write-only
P12
Output Disable
12
1
write-only
P13
Output Disable
13
1
write-only
P14
Output Disable
14
1
write-only
P15
Output Disable
15
1
write-only
P16
Output Disable
16
1
write-only
P17
Output Disable
17
1
write-only
P18
Output Disable
18
1
write-only
P19
Output Disable
19
1
write-only
P2
Output Disable
2
1
write-only
P20
Output Disable
20
1
write-only
P21
Output Disable
21
1
write-only
P22
Output Disable
22
1
write-only
P23
Output Disable
23
1
write-only
P24
Output Disable
24
1
write-only
P25
Output Disable
25
1
write-only
P26
Output Disable
26
1
write-only
P27
Output Disable
27
1
write-only
P28
Output Disable
28
1
write-only
P29
Output Disable
29
1
write-only
P3
Output Disable
3
1
write-only
P30
Output Disable
30
1
write-only
P31
Output Disable
31
1
write-only
P4
Output Disable
4
1
write-only
P5
Output Disable
5
1
write-only
P6
Output Disable
6
1
write-only
P7
Output Disable
7
1
write-only
P8
Output Disable
8
1
write-only
P9
Output Disable
9
1
write-only
ODSR
Output Data Status Register
0x38
32
read-write
n
0x0
0x0
P0
Output Data Status
0
1
read-write
P1
Output Data Status
1
1
read-write
P10
Output Data Status
10
1
read-write
P11
Output Data Status
11
1
read-write
P12
Output Data Status
12
1
read-write
P13
Output Data Status
13
1
read-write
P14
Output Data Status
14
1
read-write
P15
Output Data Status
15
1
read-write
P16
Output Data Status
16
1
read-write
P17
Output Data Status
17
1
read-write
P18
Output Data Status
18
1
read-write
P19
Output Data Status
19
1
read-write
P2
Output Data Status
2
1
read-write
P20
Output Data Status
20
1
read-write
P21
Output Data Status
21
1
read-write
P22
Output Data Status
22
1
read-write
P23
Output Data Status
23
1
read-write
P24
Output Data Status
24
1
read-write
P25
Output Data Status
25
1
read-write
P26
Output Data Status
26
1
read-write
P27
Output Data Status
27
1
read-write
P28
Output Data Status
28
1
read-write
P29
Output Data Status
29
1
read-write
P3
Output Data Status
3
1
read-write
P30
Output Data Status
30
1
read-write
P31
Output Data Status
31
1
read-write
P4
Output Data Status
4
1
read-write
P5
Output Data Status
5
1
read-write
P6
Output Data Status
6
1
read-write
P7
Output Data Status
7
1
read-write
P8
Output Data Status
8
1
read-write
P9
Output Data Status
9
1
read-write
OER
Output Enable Register
0x10
32
write-only
n
0x0
0x0
P0
Output Enable
0
1
write-only
P1
Output Enable
1
1
write-only
P10
Output Enable
10
1
write-only
P11
Output Enable
11
1
write-only
P12
Output Enable
12
1
write-only
P13
Output Enable
13
1
write-only
P14
Output Enable
14
1
write-only
P15
Output Enable
15
1
write-only
P16
Output Enable
16
1
write-only
P17
Output Enable
17
1
write-only
P18
Output Enable
18
1
write-only
P19
Output Enable
19
1
write-only
P2
Output Enable
2
1
write-only
P20
Output Enable
20
1
write-only
P21
Output Enable
21
1
write-only
P22
Output Enable
22
1
write-only
P23
Output Enable
23
1
write-only
P24
Output Enable
24
1
write-only
P25
Output Enable
25
1
write-only
P26
Output Enable
26
1
write-only
P27
Output Enable
27
1
write-only
P28
Output Enable
28
1
write-only
P29
Output Enable
29
1
write-only
P3
Output Enable
3
1
write-only
P30
Output Enable
30
1
write-only
P31
Output Enable
31
1
write-only
P4
Output Enable
4
1
write-only
P5
Output Enable
5
1
write-only
P6
Output Enable
6
1
write-only
P7
Output Enable
7
1
write-only
P8
Output Enable
8
1
write-only
P9
Output Enable
9
1
write-only
OSR
Output Status Register
0x18
32
read-only
n
0x0
0x0
P0
Output Status
0
1
read-only
P1
Output Status
1
1
read-only
P10
Output Status
10
1
read-only
P11
Output Status
11
1
read-only
P12
Output Status
12
1
read-only
P13
Output Status
13
1
read-only
P14
Output Status
14
1
read-only
P15
Output Status
15
1
read-only
P16
Output Status
16
1
read-only
P17
Output Status
17
1
read-only
P18
Output Status
18
1
read-only
P19
Output Status
19
1
read-only
P2
Output Status
2
1
read-only
P20
Output Status
20
1
read-only
P21
Output Status
21
1
read-only
P22
Output Status
22
1
read-only
P23
Output Status
23
1
read-only
P24
Output Status
24
1
read-only
P25
Output Status
25
1
read-only
P26
Output Status
26
1
read-only
P27
Output Status
27
1
read-only
P28
Output Status
28
1
read-only
P29
Output Status
29
1
read-only
P3
Output Status
3
1
read-only
P30
Output Status
30
1
read-only
P31
Output Status
31
1
read-only
P4
Output Status
4
1
read-only
P5
Output Status
5
1
read-only
P6
Output Status
6
1
read-only
P7
Output Status
7
1
read-only
P8
Output Status
8
1
read-only
P9
Output Status
9
1
read-only
OWDR
Output Write Disable
0xA4
32
write-only
n
0x0
0x0
P0
Output Write Disable
0
1
write-only
P1
Output Write Disable
1
1
write-only
P10
Output Write Disable
10
1
write-only
P11
Output Write Disable
11
1
write-only
P12
Output Write Disable
12
1
write-only
P13
Output Write Disable
13
1
write-only
P14
Output Write Disable
14
1
write-only
P15
Output Write Disable
15
1
write-only
P16
Output Write Disable
16
1
write-only
P17
Output Write Disable
17
1
write-only
P18
Output Write Disable
18
1
write-only
P19
Output Write Disable
19
1
write-only
P2
Output Write Disable
2
1
write-only
P20
Output Write Disable
20
1
write-only
P21
Output Write Disable
21
1
write-only
P22
Output Write Disable
22
1
write-only
P23
Output Write Disable
23
1
write-only
P24
Output Write Disable
24
1
write-only
P25
Output Write Disable
25
1
write-only
P26
Output Write Disable
26
1
write-only
P27
Output Write Disable
27
1
write-only
P28
Output Write Disable
28
1
write-only
P29
Output Write Disable
29
1
write-only
P3
Output Write Disable
3
1
write-only
P30
Output Write Disable
30
1
write-only
P31
Output Write Disable
31
1
write-only
P4
Output Write Disable
4
1
write-only
P5
Output Write Disable
5
1
write-only
P6
Output Write Disable
6
1
write-only
P7
Output Write Disable
7
1
write-only
P8
Output Write Disable
8
1
write-only
P9
Output Write Disable
9
1
write-only
OWER
Output Write Enable
0xA0
32
write-only
n
0x0
0x0
P0
Output Write Enable
0
1
write-only
P1
Output Write Enable
1
1
write-only
P10
Output Write Enable
10
1
write-only
P11
Output Write Enable
11
1
write-only
P12
Output Write Enable
12
1
write-only
P13
Output Write Enable
13
1
write-only
P14
Output Write Enable
14
1
write-only
P15
Output Write Enable
15
1
write-only
P16
Output Write Enable
16
1
write-only
P17
Output Write Enable
17
1
write-only
P18
Output Write Enable
18
1
write-only
P19
Output Write Enable
19
1
write-only
P2
Output Write Enable
2
1
write-only
P20
Output Write Enable
20
1
write-only
P21
Output Write Enable
21
1
write-only
P22
Output Write Enable
22
1
write-only
P23
Output Write Enable
23
1
write-only
P24
Output Write Enable
24
1
write-only
P25
Output Write Enable
25
1
write-only
P26
Output Write Enable
26
1
write-only
P27
Output Write Enable
27
1
write-only
P28
Output Write Enable
28
1
write-only
P29
Output Write Enable
29
1
write-only
P3
Output Write Enable
3
1
write-only
P30
Output Write Enable
30
1
write-only
P31
Output Write Enable
31
1
write-only
P4
Output Write Enable
4
1
write-only
P5
Output Write Enable
5
1
write-only
P6
Output Write Enable
6
1
write-only
P7
Output Write Enable
7
1
write-only
P8
Output Write Enable
8
1
write-only
P9
Output Write Enable
9
1
write-only
OWSR
Output Write Status Register
0xA8
32
read-only
n
0x0
0x0
P0
Output Write Status
0
1
read-only
P1
Output Write Status
1
1
read-only
P10
Output Write Status
10
1
read-only
P11
Output Write Status
11
1
read-only
P12
Output Write Status
12
1
read-only
P13
Output Write Status
13
1
read-only
P14
Output Write Status
14
1
read-only
P15
Output Write Status
15
1
read-only
P16
Output Write Status
16
1
read-only
P17
Output Write Status
17
1
read-only
P18
Output Write Status
18
1
read-only
P19
Output Write Status
19
1
read-only
P2
Output Write Status
2
1
read-only
P20
Output Write Status
20
1
read-only
P21
Output Write Status
21
1
read-only
P22
Output Write Status
22
1
read-only
P23
Output Write Status
23
1
read-only
P24
Output Write Status
24
1
read-only
P25
Output Write Status
25
1
read-only
P26
Output Write Status
26
1
read-only
P27
Output Write Status
27
1
read-only
P28
Output Write Status
28
1
read-only
P29
Output Write Status
29
1
read-only
P3
Output Write Status
3
1
read-only
P30
Output Write Status
30
1
read-only
P31
Output Write Status
31
1
read-only
P4
Output Write Status
4
1
read-only
P5
Output Write Status
5
1
read-only
P6
Output Write Status
6
1
read-only
P7
Output Write Status
7
1
read-only
P8
Output Write Status
8
1
read-only
P9
Output Write Status
9
1
read-only
PDR
PIO Disable Register
0x4
32
write-only
n
0x0
0x0
P0
PIO Disable
0
1
write-only
P1
PIO Disable
1
1
write-only
P10
PIO Disable
10
1
write-only
P11
PIO Disable
11
1
write-only
P12
PIO Disable
12
1
write-only
P13
PIO Disable
13
1
write-only
P14
PIO Disable
14
1
write-only
P15
PIO Disable
15
1
write-only
P16
PIO Disable
16
1
write-only
P17
PIO Disable
17
1
write-only
P18
PIO Disable
18
1
write-only
P19
PIO Disable
19
1
write-only
P2
PIO Disable
2
1
write-only
P20
PIO Disable
20
1
write-only
P21
PIO Disable
21
1
write-only
P22
PIO Disable
22
1
write-only
P23
PIO Disable
23
1
write-only
P24
PIO Disable
24
1
write-only
P25
PIO Disable
25
1
write-only
P26
PIO Disable
26
1
write-only
P27
PIO Disable
27
1
write-only
P28
PIO Disable
28
1
write-only
P29
PIO Disable
29
1
write-only
P3
PIO Disable
3
1
write-only
P30
PIO Disable
30
1
write-only
P31
PIO Disable
31
1
write-only
P4
PIO Disable
4
1
write-only
P5
PIO Disable
5
1
write-only
P6
PIO Disable
6
1
write-only
P7
PIO Disable
7
1
write-only
P8
PIO Disable
8
1
write-only
P9
PIO Disable
9
1
write-only
PDSR
Pin Data Status Register
0x3C
32
read-only
n
0x0
0x0
P0
Output Data Status
0
1
read-only
P1
Output Data Status
1
1
read-only
P10
Output Data Status
10
1
read-only
P11
Output Data Status
11
1
read-only
P12
Output Data Status
12
1
read-only
P13
Output Data Status
13
1
read-only
P14
Output Data Status
14
1
read-only
P15
Output Data Status
15
1
read-only
P16
Output Data Status
16
1
read-only
P17
Output Data Status
17
1
read-only
P18
Output Data Status
18
1
read-only
P19
Output Data Status
19
1
read-only
P2
Output Data Status
2
1
read-only
P20
Output Data Status
20
1
read-only
P21
Output Data Status
21
1
read-only
P22
Output Data Status
22
1
read-only
P23
Output Data Status
23
1
read-only
P24
Output Data Status
24
1
read-only
P25
Output Data Status
25
1
read-only
P26
Output Data Status
26
1
read-only
P27
Output Data Status
27
1
read-only
P28
Output Data Status
28
1
read-only
P29
Output Data Status
29
1
read-only
P3
Output Data Status
3
1
read-only
P30
Output Data Status
30
1
read-only
P31
Output Data Status
31
1
read-only
P4
Output Data Status
4
1
read-only
P5
Output Data Status
5
1
read-only
P6
Output Data Status
6
1
read-only
P7
Output Data Status
7
1
read-only
P8
Output Data Status
8
1
read-only
P9
Output Data Status
9
1
read-only
PER
PIO Enable Register
0x0
32
write-only
n
0x0
0x0
P0
PIO Enable
0
1
write-only
P1
PIO Enable
1
1
write-only
P10
PIO Enable
10
1
write-only
P11
PIO Enable
11
1
write-only
P12
PIO Enable
12
1
write-only
P13
PIO Enable
13
1
write-only
P14
PIO Enable
14
1
write-only
P15
PIO Enable
15
1
write-only
P16
PIO Enable
16
1
write-only
P17
PIO Enable
17
1
write-only
P18
PIO Enable
18
1
write-only
P19
PIO Enable
19
1
write-only
P2
PIO Enable
2
1
write-only
P20
PIO Enable
20
1
write-only
P21
PIO Enable
21
1
write-only
P22
PIO Enable
22
1
write-only
P23
PIO Enable
23
1
write-only
P24
PIO Enable
24
1
write-only
P25
PIO Enable
25
1
write-only
P26
PIO Enable
26
1
write-only
P27
PIO Enable
27
1
write-only
P28
PIO Enable
28
1
write-only
P29
PIO Enable
29
1
write-only
P3
PIO Enable
3
1
write-only
P30
PIO Enable
30
1
write-only
P31
PIO Enable
31
1
write-only
P4
PIO Enable
4
1
write-only
P5
PIO Enable
5
1
write-only
P6
PIO Enable
6
1
write-only
P7
PIO Enable
7
1
write-only
P8
PIO Enable
8
1
write-only
P9
PIO Enable
9
1
write-only
PPDDR
Pad Pull-down Disable Register
0x90
32
write-only
n
0x0
0x0
P0
Pull-Down Disable
0
1
write-only
P1
Pull-Down Disable
1
1
write-only
P10
Pull-Down Disable
10
1
write-only
P11
Pull-Down Disable
11
1
write-only
P12
Pull-Down Disable
12
1
write-only
P13
Pull-Down Disable
13
1
write-only
P14
Pull-Down Disable
14
1
write-only
P15
Pull-Down Disable
15
1
write-only
P16
Pull-Down Disable
16
1
write-only
P17
Pull-Down Disable
17
1
write-only
P18
Pull-Down Disable
18
1
write-only
P19
Pull-Down Disable
19
1
write-only
P2
Pull-Down Disable
2
1
write-only
P20
Pull-Down Disable
20
1
write-only
P21
Pull-Down Disable
21
1
write-only
P22
Pull-Down Disable
22
1
write-only
P23
Pull-Down Disable
23
1
write-only
P24
Pull-Down Disable
24
1
write-only
P25
Pull-Down Disable
25
1
write-only
P26
Pull-Down Disable
26
1
write-only
P27
Pull-Down Disable
27
1
write-only
P28
Pull-Down Disable
28
1
write-only
P29
Pull-Down Disable
29
1
write-only
P3
Pull-Down Disable
3
1
write-only
P30
Pull-Down Disable
30
1
write-only
P31
Pull-Down Disable
31
1
write-only
P4
Pull-Down Disable
4
1
write-only
P5
Pull-Down Disable
5
1
write-only
P6
Pull-Down Disable
6
1
write-only
P7
Pull-Down Disable
7
1
write-only
P8
Pull-Down Disable
8
1
write-only
P9
Pull-Down Disable
9
1
write-only
PPDER
Pad Pull-down Enable Register
0x94
32
write-only
n
0x0
0x0
P0
Pull-Down Enable
0
1
write-only
P1
Pull-Down Enable
1
1
write-only
P10
Pull-Down Enable
10
1
write-only
P11
Pull-Down Enable
11
1
write-only
P12
Pull-Down Enable
12
1
write-only
P13
Pull-Down Enable
13
1
write-only
P14
Pull-Down Enable
14
1
write-only
P15
Pull-Down Enable
15
1
write-only
P16
Pull-Down Enable
16
1
write-only
P17
Pull-Down Enable
17
1
write-only
P18
Pull-Down Enable
18
1
write-only
P19
Pull-Down Enable
19
1
write-only
P2
Pull-Down Enable
2
1
write-only
P20
Pull-Down Enable
20
1
write-only
P21
Pull-Down Enable
21
1
write-only
P22
Pull-Down Enable
22
1
write-only
P23
Pull-Down Enable
23
1
write-only
P24
Pull-Down Enable
24
1
write-only
P25
Pull-Down Enable
25
1
write-only
P26
Pull-Down Enable
26
1
write-only
P27
Pull-Down Enable
27
1
write-only
P28
Pull-Down Enable
28
1
write-only
P29
Pull-Down Enable
29
1
write-only
P3
Pull-Down Enable
3
1
write-only
P30
Pull-Down Enable
30
1
write-only
P31
Pull-Down Enable
31
1
write-only
P4
Pull-Down Enable
4
1
write-only
P5
Pull-Down Enable
5
1
write-only
P6
Pull-Down Enable
6
1
write-only
P7
Pull-Down Enable
7
1
write-only
P8
Pull-Down Enable
8
1
write-only
P9
Pull-Down Enable
9
1
write-only
PPDSR
Pad Pull-down Status Register
0x98
32
read-only
n
0x0
0x0
P0
Pull-Down Status
0
1
read-only
P1
Pull-Down Status
1
1
read-only
P10
Pull-Down Status
10
1
read-only
P11
Pull-Down Status
11
1
read-only
P12
Pull-Down Status
12
1
read-only
P13
Pull-Down Status
13
1
read-only
P14
Pull-Down Status
14
1
read-only
P15
Pull-Down Status
15
1
read-only
P16
Pull-Down Status
16
1
read-only
P17
Pull-Down Status
17
1
read-only
P18
Pull-Down Status
18
1
read-only
P19
Pull-Down Status
19
1
read-only
P2
Pull-Down Status
2
1
read-only
P20
Pull-Down Status
20
1
read-only
P21
Pull-Down Status
21
1
read-only
P22
Pull-Down Status
22
1
read-only
P23
Pull-Down Status
23
1
read-only
P24
Pull-Down Status
24
1
read-only
P25
Pull-Down Status
25
1
read-only
P26
Pull-Down Status
26
1
read-only
P27
Pull-Down Status
27
1
read-only
P28
Pull-Down Status
28
1
read-only
P29
Pull-Down Status
29
1
read-only
P3
Pull-Down Status
3
1
read-only
P30
Pull-Down Status
30
1
read-only
P31
Pull-Down Status
31
1
read-only
P4
Pull-Down Status
4
1
read-only
P5
Pull-Down Status
5
1
read-only
P6
Pull-Down Status
6
1
read-only
P7
Pull-Down Status
7
1
read-only
P8
Pull-Down Status
8
1
read-only
P9
Pull-Down Status
9
1
read-only
PSR
PIO Status Register
0x8
32
read-only
n
0x0
0x0
P0
PIO Status
0
1
read-only
P1
PIO Status
1
1
read-only
P10
PIO Status
10
1
read-only
P11
PIO Status
11
1
read-only
P12
PIO Status
12
1
read-only
P13
PIO Status
13
1
read-only
P14
PIO Status
14
1
read-only
P15
PIO Status
15
1
read-only
P16
PIO Status
16
1
read-only
P17
PIO Status
17
1
read-only
P18
PIO Status
18
1
read-only
P19
PIO Status
19
1
read-only
P2
PIO Status
2
1
read-only
P20
PIO Status
20
1
read-only
P21
PIO Status
21
1
read-only
P22
PIO Status
22
1
read-only
P23
PIO Status
23
1
read-only
P24
PIO Status
24
1
read-only
P25
PIO Status
25
1
read-only
P26
PIO Status
26
1
read-only
P27
PIO Status
27
1
read-only
P28
PIO Status
28
1
read-only
P29
PIO Status
29
1
read-only
P3
PIO Status
3
1
read-only
P30
PIO Status
30
1
read-only
P31
PIO Status
31
1
read-only
P4
PIO Status
4
1
read-only
P5
PIO Status
5
1
read-only
P6
PIO Status
6
1
read-only
P7
PIO Status
7
1
read-only
P8
PIO Status
8
1
read-only
P9
PIO Status
9
1
read-only
PUDR
Pull-up Disable Register
0x60
32
write-only
n
0x0
0x0
P0
Pull-Up Disable
0
1
write-only
P1
Pull-Up Disable
1
1
write-only
P10
Pull-Up Disable
10
1
write-only
P11
Pull-Up Disable
11
1
write-only
P12
Pull-Up Disable
12
1
write-only
P13
Pull-Up Disable
13
1
write-only
P14
Pull-Up Disable
14
1
write-only
P15
Pull-Up Disable
15
1
write-only
P16
Pull-Up Disable
16
1
write-only
P17
Pull-Up Disable
17
1
write-only
P18
Pull-Up Disable
18
1
write-only
P19
Pull-Up Disable
19
1
write-only
P2
Pull-Up Disable
2
1
write-only
P20
Pull-Up Disable
20
1
write-only
P21
Pull-Up Disable
21
1
write-only
P22
Pull-Up Disable
22
1
write-only
P23
Pull-Up Disable
23
1
write-only
P24
Pull-Up Disable
24
1
write-only
P25
Pull-Up Disable
25
1
write-only
P26
Pull-Up Disable
26
1
write-only
P27
Pull-Up Disable
27
1
write-only
P28
Pull-Up Disable
28
1
write-only
P29
Pull-Up Disable
29
1
write-only
P3
Pull-Up Disable
3
1
write-only
P30
Pull-Up Disable
30
1
write-only
P31
Pull-Up Disable
31
1
write-only
P4
Pull-Up Disable
4
1
write-only
P5
Pull-Up Disable
5
1
write-only
P6
Pull-Up Disable
6
1
write-only
P7
Pull-Up Disable
7
1
write-only
P8
Pull-Up Disable
8
1
write-only
P9
Pull-Up Disable
9
1
write-only
PUER
Pull-up Enable Register
0x64
32
write-only
n
0x0
0x0
P0
Pull-Up Enable
0
1
write-only
P1
Pull-Up Enable
1
1
write-only
P10
Pull-Up Enable
10
1
write-only
P11
Pull-Up Enable
11
1
write-only
P12
Pull-Up Enable
12
1
write-only
P13
Pull-Up Enable
13
1
write-only
P14
Pull-Up Enable
14
1
write-only
P15
Pull-Up Enable
15
1
write-only
P16
Pull-Up Enable
16
1
write-only
P17
Pull-Up Enable
17
1
write-only
P18
Pull-Up Enable
18
1
write-only
P19
Pull-Up Enable
19
1
write-only
P2
Pull-Up Enable
2
1
write-only
P20
Pull-Up Enable
20
1
write-only
P21
Pull-Up Enable
21
1
write-only
P22
Pull-Up Enable
22
1
write-only
P23
Pull-Up Enable
23
1
write-only
P24
Pull-Up Enable
24
1
write-only
P25
Pull-Up Enable
25
1
write-only
P26
Pull-Up Enable
26
1
write-only
P27
Pull-Up Enable
27
1
write-only
P28
Pull-Up Enable
28
1
write-only
P29
Pull-Up Enable
29
1
write-only
P3
Pull-Up Enable
3
1
write-only
P30
Pull-Up Enable
30
1
write-only
P31
Pull-Up Enable
31
1
write-only
P4
Pull-Up Enable
4
1
write-only
P5
Pull-Up Enable
5
1
write-only
P6
Pull-Up Enable
6
1
write-only
P7
Pull-Up Enable
7
1
write-only
P8
Pull-Up Enable
8
1
write-only
P9
Pull-Up Enable
9
1
write-only
PUSR
Pad Pull-up Status Register
0x68
32
read-only
n
0x0
0x0
P0
Pull-Up Status
0
1
read-only
P1
Pull-Up Status
1
1
read-only
P10
Pull-Up Status
10
1
read-only
P11
Pull-Up Status
11
1
read-only
P12
Pull-Up Status
12
1
read-only
P13
Pull-Up Status
13
1
read-only
P14
Pull-Up Status
14
1
read-only
P15
Pull-Up Status
15
1
read-only
P16
Pull-Up Status
16
1
read-only
P17
Pull-Up Status
17
1
read-only
P18
Pull-Up Status
18
1
read-only
P19
Pull-Up Status
19
1
read-only
P2
Pull-Up Status
2
1
read-only
P20
Pull-Up Status
20
1
read-only
P21
Pull-Up Status
21
1
read-only
P22
Pull-Up Status
22
1
read-only
P23
Pull-Up Status
23
1
read-only
P24
Pull-Up Status
24
1
read-only
P25
Pull-Up Status
25
1
read-only
P26
Pull-Up Status
26
1
read-only
P27
Pull-Up Status
27
1
read-only
P28
Pull-Up Status
28
1
read-only
P29
Pull-Up Status
29
1
read-only
P3
Pull-Up Status
3
1
read-only
P30
Pull-Up Status
30
1
read-only
P31
Pull-Up Status
31
1
read-only
P4
Pull-Up Status
4
1
read-only
P5
Pull-Up Status
5
1
read-only
P6
Pull-Up Status
6
1
read-only
P7
Pull-Up Status
7
1
read-only
P8
Pull-Up Status
8
1
read-only
P9
Pull-Up Status
9
1
read-only
REHLSR
Rising Edge/High-Level Select Register
0xD4
32
write-only
n
0x0
0x0
P0
Rising Edge/High-Level Interrupt Selection
0
1
write-only
P1
Rising Edge/High-Level Interrupt Selection
1
1
write-only
P10
Rising Edge/High-Level Interrupt Selection
10
1
write-only
P11
Rising Edge/High-Level Interrupt Selection
11
1
write-only
P12
Rising Edge/High-Level Interrupt Selection
12
1
write-only
P13
Rising Edge/High-Level Interrupt Selection
13
1
write-only
P14
Rising Edge/High-Level Interrupt Selection
14
1
write-only
P15
Rising Edge/High-Level Interrupt Selection
15
1
write-only
P16
Rising Edge/High-Level Interrupt Selection
16
1
write-only
P17
Rising Edge/High-Level Interrupt Selection
17
1
write-only
P18
Rising Edge/High-Level Interrupt Selection
18
1
write-only
P19
Rising Edge/High-Level Interrupt Selection
19
1
write-only
P2
Rising Edge/High-Level Interrupt Selection
2
1
write-only
P20
Rising Edge/High-Level Interrupt Selection
20
1
write-only
P21
Rising Edge/High-Level Interrupt Selection
21
1
write-only
P22
Rising Edge/High-Level Interrupt Selection
22
1
write-only
P23
Rising Edge/High-Level Interrupt Selection
23
1
write-only
P24
Rising Edge/High-Level Interrupt Selection
24
1
write-only
P25
Rising Edge/High-Level Interrupt Selection
25
1
write-only
P26
Rising Edge/High-Level Interrupt Selection
26
1
write-only
P27
Rising Edge/High-Level Interrupt Selection
27
1
write-only
P28
Rising Edge/High-Level Interrupt Selection
28
1
write-only
P29
Rising Edge/High-Level Interrupt Selection
29
1
write-only
P3
Rising Edge/High-Level Interrupt Selection
3
1
write-only
P30
Rising Edge/High-Level Interrupt Selection
30
1
write-only
P31
Rising Edge/High-Level Interrupt Selection
31
1
write-only
P4
Rising Edge/High-Level Interrupt Selection
4
1
write-only
P5
Rising Edge/High-Level Interrupt Selection
5
1
write-only
P6
Rising Edge/High-Level Interrupt Selection
6
1
write-only
P7
Rising Edge/High-Level Interrupt Selection
7
1
write-only
P8
Rising Edge/High-Level Interrupt Selection
8
1
write-only
P9
Rising Edge/High-Level Interrupt Selection
9
1
write-only
SCDR
Slow Clock Divider Debouncing Register
0x8C
32
read-write
n
0x0
0x0
DIV
Slow Clock Divider Selection for Debouncing
0
14
read-write
SCHMITT
Schmitt Trigger Register
0x100
32
read-write
n
0x0
0x0
SCHMITT0
Schmitt Trigger Control
0
1
read-write
SCHMITT1
Schmitt Trigger Control
1
1
read-write
SCHMITT10
Schmitt Trigger Control
10
1
read-write
SCHMITT11
Schmitt Trigger Control
11
1
read-write
SCHMITT12
Schmitt Trigger Control
12
1
read-write
SCHMITT13
Schmitt Trigger Control
13
1
read-write
SCHMITT14
Schmitt Trigger Control
14
1
read-write
SCHMITT15
Schmitt Trigger Control
15
1
read-write
SCHMITT16
Schmitt Trigger Control
16
1
read-write
SCHMITT17
Schmitt Trigger Control
17
1
read-write
SCHMITT18
Schmitt Trigger Control
18
1
read-write
SCHMITT19
Schmitt Trigger Control
19
1
read-write
SCHMITT2
Schmitt Trigger Control
2
1
read-write
SCHMITT20
Schmitt Trigger Control
20
1
read-write
SCHMITT21
Schmitt Trigger Control
21
1
read-write
SCHMITT22
Schmitt Trigger Control
22
1
read-write
SCHMITT23
Schmitt Trigger Control
23
1
read-write
SCHMITT24
Schmitt Trigger Control
24
1
read-write
SCHMITT25
Schmitt Trigger Control
25
1
read-write
SCHMITT26
Schmitt Trigger Control
26
1
read-write
SCHMITT27
Schmitt Trigger Control
27
1
read-write
SCHMITT28
Schmitt Trigger Control
28
1
read-write
SCHMITT29
Schmitt Trigger Control
29
1
read-write
SCHMITT3
Schmitt Trigger Control
3
1
read-write
SCHMITT30
Schmitt Trigger Control
30
1
read-write
SCHMITT31
Schmitt Trigger Control
31
1
read-write
SCHMITT4
Schmitt Trigger Control
4
1
read-write
SCHMITT5
Schmitt Trigger Control
5
1
read-write
SCHMITT6
Schmitt Trigger Control
6
1
read-write
SCHMITT7
Schmitt Trigger Control
7
1
read-write
SCHMITT8
Schmitt Trigger Control
8
1
read-write
SCHMITT9
Schmitt Trigger Control
9
1
read-write
SODR
Set Output Data Register
0x30
32
write-only
n
0x0
0x0
P0
Set Output Data
0
1
write-only
P1
Set Output Data
1
1
write-only
P10
Set Output Data
10
1
write-only
P11
Set Output Data
11
1
write-only
P12
Set Output Data
12
1
write-only
P13
Set Output Data
13
1
write-only
P14
Set Output Data
14
1
write-only
P15
Set Output Data
15
1
write-only
P16
Set Output Data
16
1
write-only
P17
Set Output Data
17
1
write-only
P18
Set Output Data
18
1
write-only
P19
Set Output Data
19
1
write-only
P2
Set Output Data
2
1
write-only
P20
Set Output Data
20
1
write-only
P21
Set Output Data
21
1
write-only
P22
Set Output Data
22
1
write-only
P23
Set Output Data
23
1
write-only
P24
Set Output Data
24
1
write-only
P25
Set Output Data
25
1
write-only
P26
Set Output Data
26
1
write-only
P27
Set Output Data
27
1
write-only
P28
Set Output Data
28
1
write-only
P29
Set Output Data
29
1
write-only
P3
Set Output Data
3
1
write-only
P30
Set Output Data
30
1
write-only
P31
Set Output Data
31
1
write-only
P4
Set Output Data
4
1
write-only
P5
Set Output Data
5
1
write-only
P6
Set Output Data
6
1
write-only
P7
Set Output Data
7
1
write-only
P8
Set Output Data
8
1
write-only
P9
Set Output Data
9
1
write-only
WPMR
Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protection Enable
0
1
read-write
WPKEY
Write Protection Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
0x50494F
WPSR
Write Protection Status Register
0xE8
32
read-only
n
0x0
0x0
WPVS
Write Protection Violation Status
0
1
read-only
WPVSRC
Write Protection Violation Source
8
16
read-only
PIOC
Parallel Input/Output Controller C
PIO
0x0
0x0
0x50
registers
n
PIOC
37
ABCDSR0
Peripheral Select Register
0x70
32
read-write
n
P0
Peripheral Select
0
1
read-write
P1
Peripheral Select
1
1
read-write
P10
Peripheral Select
10
1
read-write
P11
Peripheral Select
11
1
read-write
P12
Peripheral Select
12
1
read-write
P13
Peripheral Select
13
1
read-write
P14
Peripheral Select
14
1
read-write
P15
Peripheral Select
15
1
read-write
P16
Peripheral Select
16
1
read-write
P17
Peripheral Select
17
1
read-write
P18
Peripheral Select
18
1
read-write
P19
Peripheral Select
19
1
read-write
P2
Peripheral Select
2
1
read-write
P20
Peripheral Select
20
1
read-write
P21
Peripheral Select
21
1
read-write
P22
Peripheral Select
22
1
read-write
P23
Peripheral Select
23
1
read-write
P24
Peripheral Select
24
1
read-write
P25
Peripheral Select
25
1
read-write
P26
Peripheral Select
26
1
read-write
P27
Peripheral Select
27
1
read-write
P28
Peripheral Select
28
1
read-write
P29
Peripheral Select
29
1
read-write
P3
Peripheral Select
3
1
read-write
P30
Peripheral Select
30
1
read-write
P31
Peripheral Select
31
1
read-write
P4
Peripheral Select
4
1
read-write
P5
Peripheral Select
5
1
read-write
P6
Peripheral Select
6
1
read-write
P7
Peripheral Select
7
1
read-write
P8
Peripheral Select
8
1
read-write
P9
Peripheral Select
9
1
read-write
ABCDSR1
Peripheral Select Register
0x74
32
read-write
n
P0
Peripheral Select
0
1
read-write
P1
Peripheral Select
1
1
read-write
P10
Peripheral Select
10
1
read-write
P11
Peripheral Select
11
1
read-write
P12
Peripheral Select
12
1
read-write
P13
Peripheral Select
13
1
read-write
P14
Peripheral Select
14
1
read-write
P15
Peripheral Select
15
1
read-write
P16
Peripheral Select
16
1
read-write
P17
Peripheral Select
17
1
read-write
P18
Peripheral Select
18
1
read-write
P19
Peripheral Select
19
1
read-write
P2
Peripheral Select
2
1
read-write
P20
Peripheral Select
20
1
read-write
P21
Peripheral Select
21
1
read-write
P22
Peripheral Select
22
1
read-write
P23
Peripheral Select
23
1
read-write
P24
Peripheral Select
24
1
read-write
P25
Peripheral Select
25
1
read-write
P26
Peripheral Select
26
1
read-write
P27
Peripheral Select
27
1
read-write
P28
Peripheral Select
28
1
read-write
P29
Peripheral Select
29
1
read-write
P3
Peripheral Select
3
1
read-write
P30
Peripheral Select
30
1
read-write
P31
Peripheral Select
31
1
read-write
P4
Peripheral Select
4
1
read-write
P5
Peripheral Select
5
1
read-write
P6
Peripheral Select
6
1
read-write
P7
Peripheral Select
7
1
read-write
P8
Peripheral Select
8
1
read-write
P9
Peripheral Select
9
1
read-write
ABCDSR[0]
Peripheral Select Register
0xE0
32
read-write
n
0x0
0x0
P0
Peripheral Select
0
1
read-write
P1
Peripheral Select
1
1
read-write
P10
Peripheral Select
10
1
read-write
P11
Peripheral Select
11
1
read-write
P12
Peripheral Select
12
1
read-write
P13
Peripheral Select
13
1
read-write
P14
Peripheral Select
14
1
read-write
P15
Peripheral Select
15
1
read-write
P16
Peripheral Select
16
1
read-write
P17
Peripheral Select
17
1
read-write
P18
Peripheral Select
18
1
read-write
P19
Peripheral Select
19
1
read-write
P2
Peripheral Select
2
1
read-write
P20
Peripheral Select
20
1
read-write
P21
Peripheral Select
21
1
read-write
P22
Peripheral Select
22
1
read-write
P23
Peripheral Select
23
1
read-write
P24
Peripheral Select
24
1
read-write
P25
Peripheral Select
25
1
read-write
P26
Peripheral Select
26
1
read-write
P27
Peripheral Select
27
1
read-write
P28
Peripheral Select
28
1
read-write
P29
Peripheral Select
29
1
read-write
P3
Peripheral Select
3
1
read-write
P30
Peripheral Select
30
1
read-write
P31
Peripheral Select
31
1
read-write
P4
Peripheral Select
4
1
read-write
P5
Peripheral Select
5
1
read-write
P6
Peripheral Select
6
1
read-write
P7
Peripheral Select
7
1
read-write
P8
Peripheral Select
8
1
read-write
P9
Peripheral Select
9
1
read-write
ABCDSR[1]
Peripheral Select Register
0x154
32
read-write
n
0x0
0x0
P0
Peripheral Select
0
1
read-write
P1
Peripheral Select
1
1
read-write
P10
Peripheral Select
10
1
read-write
P11
Peripheral Select
11
1
read-write
P12
Peripheral Select
12
1
read-write
P13
Peripheral Select
13
1
read-write
P14
Peripheral Select
14
1
read-write
P15
Peripheral Select
15
1
read-write
P16
Peripheral Select
16
1
read-write
P17
Peripheral Select
17
1
read-write
P18
Peripheral Select
18
1
read-write
P19
Peripheral Select
19
1
read-write
P2
Peripheral Select
2
1
read-write
P20
Peripheral Select
20
1
read-write
P21
Peripheral Select
21
1
read-write
P22
Peripheral Select
22
1
read-write
P23
Peripheral Select
23
1
read-write
P24
Peripheral Select
24
1
read-write
P25
Peripheral Select
25
1
read-write
P26
Peripheral Select
26
1
read-write
P27
Peripheral Select
27
1
read-write
P28
Peripheral Select
28
1
read-write
P29
Peripheral Select
29
1
read-write
P3
Peripheral Select
3
1
read-write
P30
Peripheral Select
30
1
read-write
P31
Peripheral Select
31
1
read-write
P4
Peripheral Select
4
1
read-write
P5
Peripheral Select
5
1
read-write
P6
Peripheral Select
6
1
read-write
P7
Peripheral Select
7
1
read-write
P8
Peripheral Select
8
1
read-write
P9
Peripheral Select
9
1
read-write
AIMDR
Additional Interrupt Modes Disable Register
0xB4
32
write-only
n
0x0
0x0
P0
Additional Interrupt Modes Disable
0
1
write-only
P1
Additional Interrupt Modes Disable
1
1
write-only
P10
Additional Interrupt Modes Disable
10
1
write-only
P11
Additional Interrupt Modes Disable
11
1
write-only
P12
Additional Interrupt Modes Disable
12
1
write-only
P13
Additional Interrupt Modes Disable
13
1
write-only
P14
Additional Interrupt Modes Disable
14
1
write-only
P15
Additional Interrupt Modes Disable
15
1
write-only
P16
Additional Interrupt Modes Disable
16
1
write-only
P17
Additional Interrupt Modes Disable
17
1
write-only
P18
Additional Interrupt Modes Disable
18
1
write-only
P19
Additional Interrupt Modes Disable
19
1
write-only
P2
Additional Interrupt Modes Disable
2
1
write-only
P20
Additional Interrupt Modes Disable
20
1
write-only
P21
Additional Interrupt Modes Disable
21
1
write-only
P22
Additional Interrupt Modes Disable
22
1
write-only
P23
Additional Interrupt Modes Disable
23
1
write-only
P24
Additional Interrupt Modes Disable
24
1
write-only
P25
Additional Interrupt Modes Disable
25
1
write-only
P26
Additional Interrupt Modes Disable
26
1
write-only
P27
Additional Interrupt Modes Disable
27
1
write-only
P28
Additional Interrupt Modes Disable
28
1
write-only
P29
Additional Interrupt Modes Disable
29
1
write-only
P3
Additional Interrupt Modes Disable
3
1
write-only
P30
Additional Interrupt Modes Disable
30
1
write-only
P31
Additional Interrupt Modes Disable
31
1
write-only
P4
Additional Interrupt Modes Disable
4
1
write-only
P5
Additional Interrupt Modes Disable
5
1
write-only
P6
Additional Interrupt Modes Disable
6
1
write-only
P7
Additional Interrupt Modes Disable
7
1
write-only
P8
Additional Interrupt Modes Disable
8
1
write-only
P9
Additional Interrupt Modes Disable
9
1
write-only
AIMER
Additional Interrupt Modes Enable Register
0xB0
32
write-only
n
0x0
0x0
P0
Additional Interrupt Modes Enable
0
1
write-only
P1
Additional Interrupt Modes Enable
1
1
write-only
P10
Additional Interrupt Modes Enable
10
1
write-only
P11
Additional Interrupt Modes Enable
11
1
write-only
P12
Additional Interrupt Modes Enable
12
1
write-only
P13
Additional Interrupt Modes Enable
13
1
write-only
P14
Additional Interrupt Modes Enable
14
1
write-only
P15
Additional Interrupt Modes Enable
15
1
write-only
P16
Additional Interrupt Modes Enable
16
1
write-only
P17
Additional Interrupt Modes Enable
17
1
write-only
P18
Additional Interrupt Modes Enable
18
1
write-only
P19
Additional Interrupt Modes Enable
19
1
write-only
P2
Additional Interrupt Modes Enable
2
1
write-only
P20
Additional Interrupt Modes Enable
20
1
write-only
P21
Additional Interrupt Modes Enable
21
1
write-only
P22
Additional Interrupt Modes Enable
22
1
write-only
P23
Additional Interrupt Modes Enable
23
1
write-only
P24
Additional Interrupt Modes Enable
24
1
write-only
P25
Additional Interrupt Modes Enable
25
1
write-only
P26
Additional Interrupt Modes Enable
26
1
write-only
P27
Additional Interrupt Modes Enable
27
1
write-only
P28
Additional Interrupt Modes Enable
28
1
write-only
P29
Additional Interrupt Modes Enable
29
1
write-only
P3
Additional Interrupt Modes Enable
3
1
write-only
P30
Additional Interrupt Modes Enable
30
1
write-only
P31
Additional Interrupt Modes Enable
31
1
write-only
P4
Additional Interrupt Modes Enable
4
1
write-only
P5
Additional Interrupt Modes Enable
5
1
write-only
P6
Additional Interrupt Modes Enable
6
1
write-only
P7
Additional Interrupt Modes Enable
7
1
write-only
P8
Additional Interrupt Modes Enable
8
1
write-only
P9
Additional Interrupt Modes Enable
9
1
write-only
AIMMR
Additional Interrupt Modes Mask Register
0xB8
32
read-only
n
0x0
0x0
P0
IO Line Index
0
1
read-only
P1
IO Line Index
1
1
read-only
P10
IO Line Index
10
1
read-only
P11
IO Line Index
11
1
read-only
P12
IO Line Index
12
1
read-only
P13
IO Line Index
13
1
read-only
P14
IO Line Index
14
1
read-only
P15
IO Line Index
15
1
read-only
P16
IO Line Index
16
1
read-only
P17
IO Line Index
17
1
read-only
P18
IO Line Index
18
1
read-only
P19
IO Line Index
19
1
read-only
P2
IO Line Index
2
1
read-only
P20
IO Line Index
20
1
read-only
P21
IO Line Index
21
1
read-only
P22
IO Line Index
22
1
read-only
P23
IO Line Index
23
1
read-only
P24
IO Line Index
24
1
read-only
P25
IO Line Index
25
1
read-only
P26
IO Line Index
26
1
read-only
P27
IO Line Index
27
1
read-only
P28
IO Line Index
28
1
read-only
P29
IO Line Index
29
1
read-only
P3
IO Line Index
3
1
read-only
P30
IO Line Index
30
1
read-only
P31
IO Line Index
31
1
read-only
P4
IO Line Index
4
1
read-only
P5
IO Line Index
5
1
read-only
P6
IO Line Index
6
1
read-only
P7
IO Line Index
7
1
read-only
P8
IO Line Index
8
1
read-only
P9
IO Line Index
9
1
read-only
CODR
Clear Output Data Register
0x34
32
write-only
n
0x0
0x0
P0
Clear Output Data
0
1
write-only
P1
Clear Output Data
1
1
write-only
P10
Clear Output Data
10
1
write-only
P11
Clear Output Data
11
1
write-only
P12
Clear Output Data
12
1
write-only
P13
Clear Output Data
13
1
write-only
P14
Clear Output Data
14
1
write-only
P15
Clear Output Data
15
1
write-only
P16
Clear Output Data
16
1
write-only
P17
Clear Output Data
17
1
write-only
P18
Clear Output Data
18
1
write-only
P19
Clear Output Data
19
1
write-only
P2
Clear Output Data
2
1
write-only
P20
Clear Output Data
20
1
write-only
P21
Clear Output Data
21
1
write-only
P22
Clear Output Data
22
1
write-only
P23
Clear Output Data
23
1
write-only
P24
Clear Output Data
24
1
write-only
P25
Clear Output Data
25
1
write-only
P26
Clear Output Data
26
1
write-only
P27
Clear Output Data
27
1
write-only
P28
Clear Output Data
28
1
write-only
P29
Clear Output Data
29
1
write-only
P3
Clear Output Data
3
1
write-only
P30
Clear Output Data
30
1
write-only
P31
Clear Output Data
31
1
write-only
P4
Clear Output Data
4
1
write-only
P5
Clear Output Data
5
1
write-only
P6
Clear Output Data
6
1
write-only
P7
Clear Output Data
7
1
write-only
P8
Clear Output Data
8
1
write-only
P9
Clear Output Data
9
1
write-only
DRIVER
I/O Drive Register
0x118
32
read-write
n
0x0
0x0
LINE0
Drive of PIO Line 0
0
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE1
Drive of PIO Line 1
1
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE10
Drive of PIO Line 10
10
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE11
Drive of PIO Line 11
11
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE12
Drive of PIO Line 12
12
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE13
Drive of PIO Line 13
13
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE14
Drive of PIO Line 14
14
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE15
Drive of PIO Line 15
15
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE16
Drive of PIO Line 16
16
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE17
Drive of PIO Line 17
17
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE18
Drive of PIO Line 18
18
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE19
Drive of PIO Line 19
19
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE2
Drive of PIO Line 2
2
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE20
Drive of PIO Line 20
20
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE21
Drive of PIO Line 21
21
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE22
Drive of PIO Line 22
22
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE23
Drive of PIO Line 23
23
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE24
Drive of PIO Line 24
24
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE25
Drive of PIO Line 25
25
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE26
Drive of PIO Line 26
26
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE27
Drive of PIO Line 27
27
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE28
Drive of PIO Line 28
28
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE29
Drive of PIO Line 29
29
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE3
Drive of PIO Line 3
3
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE30
Drive of PIO Line 30
30
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE31
Drive of PIO Line 31
31
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE4
Drive of PIO Line 4
4
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE5
Drive of PIO Line 5
5
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE6
Drive of PIO Line 6
6
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE7
Drive of PIO Line 7
7
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE8
Drive of PIO Line 8
8
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
LINE9
Drive of PIO Line 9
9
1
read-write
LOW_DRIVE
Lowest drive
0
HIGH_DRIVE
Highest drive
1
ELSR
Edge/Level Status Register
0xC8
32
read-only
n
0x0
0x0
P0
Edge/Level Interrupt Source Selection
0
1
read-only
P1
Edge/Level Interrupt Source Selection
1
1
read-only
P10
Edge/Level Interrupt Source Selection
10
1
read-only
P11
Edge/Level Interrupt Source Selection
11
1
read-only
P12
Edge/Level Interrupt Source Selection
12
1
read-only
P13
Edge/Level Interrupt Source Selection
13
1
read-only
P14
Edge/Level Interrupt Source Selection
14
1
read-only
P15
Edge/Level Interrupt Source Selection
15
1
read-only
P16
Edge/Level Interrupt Source Selection
16
1
read-only
P17
Edge/Level Interrupt Source Selection
17
1
read-only
P18
Edge/Level Interrupt Source Selection
18
1
read-only
P19
Edge/Level Interrupt Source Selection
19
1
read-only
P2
Edge/Level Interrupt Source Selection
2
1
read-only
P20
Edge/Level Interrupt Source Selection
20
1
read-only
P21
Edge/Level Interrupt Source Selection
21
1
read-only
P22
Edge/Level Interrupt Source Selection
22
1
read-only
P23
Edge/Level Interrupt Source Selection
23
1
read-only
P24
Edge/Level Interrupt Source Selection
24
1
read-only
P25
Edge/Level Interrupt Source Selection
25
1
read-only
P26
Edge/Level Interrupt Source Selection
26
1
read-only
P27
Edge/Level Interrupt Source Selection
27
1
read-only
P28
Edge/Level Interrupt Source Selection
28
1
read-only
P29
Edge/Level Interrupt Source Selection
29
1
read-only
P3
Edge/Level Interrupt Source Selection
3
1
read-only
P30
Edge/Level Interrupt Source Selection
30
1
read-only
P31
Edge/Level Interrupt Source Selection
31
1
read-only
P4
Edge/Level Interrupt Source Selection
4
1
read-only
P5
Edge/Level Interrupt Source Selection
5
1
read-only
P6
Edge/Level Interrupt Source Selection
6
1
read-only
P7
Edge/Level Interrupt Source Selection
7
1
read-only
P8
Edge/Level Interrupt Source Selection
8
1
read-only
P9
Edge/Level Interrupt Source Selection
9
1
read-only
ESR
Edge Select Register
0xC0
32
write-only
n
0x0
0x0
P0
Edge Interrupt Selection
0
1
write-only
P1
Edge Interrupt Selection
1
1
write-only
P10
Edge Interrupt Selection
10
1
write-only
P11
Edge Interrupt Selection
11
1
write-only
P12
Edge Interrupt Selection
12
1
write-only
P13
Edge Interrupt Selection
13
1
write-only
P14
Edge Interrupt Selection
14
1
write-only
P15
Edge Interrupt Selection
15
1
write-only
P16
Edge Interrupt Selection
16
1
write-only
P17
Edge Interrupt Selection
17
1
write-only
P18
Edge Interrupt Selection
18
1
write-only
P19
Edge Interrupt Selection
19
1
write-only
P2
Edge Interrupt Selection
2
1
write-only
P20
Edge Interrupt Selection
20
1
write-only
P21
Edge Interrupt Selection
21
1
write-only
P22
Edge Interrupt Selection
22
1
write-only
P23
Edge Interrupt Selection
23
1
write-only
P24
Edge Interrupt Selection
24
1
write-only
P25
Edge Interrupt Selection
25
1
write-only
P26
Edge Interrupt Selection
26
1
write-only
P27
Edge Interrupt Selection
27
1
write-only
P28
Edge Interrupt Selection
28
1
write-only
P29
Edge Interrupt Selection
29
1
write-only
P3
Edge Interrupt Selection
3
1
write-only
P30
Edge Interrupt Selection
30
1
write-only
P31
Edge Interrupt Selection
31
1
write-only
P4
Edge Interrupt Selection
4
1
write-only
P5
Edge Interrupt Selection
5
1
write-only
P6
Edge Interrupt Selection
6
1
write-only
P7
Edge Interrupt Selection
7
1
write-only
P8
Edge Interrupt Selection
8
1
write-only
P9
Edge Interrupt Selection
9
1
write-only
FELLSR
Falling Edge/Low-Level Select Register
0xD0
32
write-only
n
0x0
0x0
P0
Falling Edge/Low-Level Interrupt Selection
0
1
write-only
P1
Falling Edge/Low-Level Interrupt Selection
1
1
write-only
P10
Falling Edge/Low-Level Interrupt Selection
10
1
write-only
P11
Falling Edge/Low-Level Interrupt Selection
11
1
write-only
P12
Falling Edge/Low-Level Interrupt Selection
12
1
write-only
P13
Falling Edge/Low-Level Interrupt Selection
13
1
write-only
P14
Falling Edge/Low-Level Interrupt Selection
14
1
write-only
P15
Falling Edge/Low-Level Interrupt Selection
15
1
write-only
P16
Falling Edge/Low-Level Interrupt Selection
16
1
write-only
P17
Falling Edge/Low-Level Interrupt Selection
17
1
write-only
P18
Falling Edge/Low-Level Interrupt Selection
18
1
write-only
P19
Falling Edge/Low-Level Interrupt Selection
19
1
write-only
P2
Falling Edge/Low-Level Interrupt Selection
2
1
write-only
P20
Falling Edge/Low-Level Interrupt Selection
20
1
write-only
P21
Falling Edge/Low-Level Interrupt Selection
21
1
write-only
P22
Falling Edge/Low-Level Interrupt Selection
22
1
write-only
P23
Falling Edge/Low-Level Interrupt Selection
23
1
write-only
P24
Falling Edge/Low-Level Interrupt Selection
24
1
write-only
P25
Falling Edge/Low-Level Interrupt Selection
25
1
write-only
P26
Falling Edge/Low-Level Interrupt Selection
26
1
write-only
P27
Falling Edge/Low-Level Interrupt Selection
27
1
write-only
P28
Falling Edge/Low-Level Interrupt Selection
28
1
write-only
P29
Falling Edge/Low-Level Interrupt Selection
29
1
write-only
P3
Falling Edge/Low-Level Interrupt Selection
3
1
write-only
P30
Falling Edge/Low-Level Interrupt Selection
30
1
write-only
P31
Falling Edge/Low-Level Interrupt Selection
31
1
write-only
P4
Falling Edge/Low-Level Interrupt Selection
4
1
write-only
P5
Falling Edge/Low-Level Interrupt Selection
5
1
write-only
P6
Falling Edge/Low-Level Interrupt Selection
6
1
write-only
P7
Falling Edge/Low-Level Interrupt Selection
7
1
write-only
P8
Falling Edge/Low-Level Interrupt Selection
8
1
write-only
P9
Falling Edge/Low-Level Interrupt Selection
9
1
write-only
FRLHSR
Fall/Rise - Low/High Status Register
0xD8
32
read-only
n
0x0
0x0
P0
Edge/Level Interrupt Source Selection
0
1
read-only
P1
Edge/Level Interrupt Source Selection
1
1
read-only
P10
Edge/Level Interrupt Source Selection
10
1
read-only
P11
Edge/Level Interrupt Source Selection
11
1
read-only
P12
Edge/Level Interrupt Source Selection
12
1
read-only
P13
Edge/Level Interrupt Source Selection
13
1
read-only
P14
Edge/Level Interrupt Source Selection
14
1
read-only
P15
Edge/Level Interrupt Source Selection
15
1
read-only
P16
Edge/Level Interrupt Source Selection
16
1
read-only
P17
Edge/Level Interrupt Source Selection
17
1
read-only
P18
Edge/Level Interrupt Source Selection
18
1
read-only
P19
Edge/Level Interrupt Source Selection
19
1
read-only
P2
Edge/Level Interrupt Source Selection
2
1
read-only
P20
Edge/Level Interrupt Source Selection
20
1
read-only
P21
Edge/Level Interrupt Source Selection
21
1
read-only
P22
Edge/Level Interrupt Source Selection
22
1
read-only
P23
Edge/Level Interrupt Source Selection
23
1
read-only
P24
Edge/Level Interrupt Source Selection
24
1
read-only
P25
Edge/Level Interrupt Source Selection
25
1
read-only
P26
Edge/Level Interrupt Source Selection
26
1
read-only
P27
Edge/Level Interrupt Source Selection
27
1
read-only
P28
Edge/Level Interrupt Source Selection
28
1
read-only
P29
Edge/Level Interrupt Source Selection
29
1
read-only
P3
Edge/Level Interrupt Source Selection
3
1
read-only
P30
Edge/Level Interrupt Source Selection
30
1
read-only
P31
Edge/Level Interrupt Source Selection
31
1
read-only
P4
Edge/Level Interrupt Source Selection
4
1
read-only
P5
Edge/Level Interrupt Source Selection
5
1
read-only
P6
Edge/Level Interrupt Source Selection
6
1
read-only
P7
Edge/Level Interrupt Source Selection
7
1
read-only
P8
Edge/Level Interrupt Source Selection
8
1
read-only
P9
Edge/Level Interrupt Source Selection
9
1
read-only
IDR
Interrupt Disable Register
0x44
32
write-only
n
0x0
0x0
P0
Input Change Interrupt Disable
0
1
write-only
P1
Input Change Interrupt Disable
1
1
write-only
P10
Input Change Interrupt Disable
10
1
write-only
P11
Input Change Interrupt Disable
11
1
write-only
P12
Input Change Interrupt Disable
12
1
write-only
P13
Input Change Interrupt Disable
13
1
write-only
P14
Input Change Interrupt Disable
14
1
write-only
P15
Input Change Interrupt Disable
15
1
write-only
P16
Input Change Interrupt Disable
16
1
write-only
P17
Input Change Interrupt Disable
17
1
write-only
P18
Input Change Interrupt Disable
18
1
write-only
P19
Input Change Interrupt Disable
19
1
write-only
P2
Input Change Interrupt Disable
2
1
write-only
P20
Input Change Interrupt Disable
20
1
write-only
P21
Input Change Interrupt Disable
21
1
write-only
P22
Input Change Interrupt Disable
22
1
write-only
P23
Input Change Interrupt Disable
23
1
write-only
P24
Input Change Interrupt Disable
24
1
write-only
P25
Input Change Interrupt Disable
25
1
write-only
P26
Input Change Interrupt Disable
26
1
write-only
P27
Input Change Interrupt Disable
27
1
write-only
P28
Input Change Interrupt Disable
28
1
write-only
P29
Input Change Interrupt Disable
29
1
write-only
P3
Input Change Interrupt Disable
3
1
write-only
P30
Input Change Interrupt Disable
30
1
write-only
P31
Input Change Interrupt Disable
31
1
write-only
P4
Input Change Interrupt Disable
4
1
write-only
P5
Input Change Interrupt Disable
5
1
write-only
P6
Input Change Interrupt Disable
6
1
write-only
P7
Input Change Interrupt Disable
7
1
write-only
P8
Input Change Interrupt Disable
8
1
write-only
P9
Input Change Interrupt Disable
9
1
write-only
IER
Interrupt Enable Register
0x40
32
write-only
n
0x0
0x0
P0
Input Change Interrupt Enable
0
1
write-only
P1
Input Change Interrupt Enable
1
1
write-only
P10
Input Change Interrupt Enable
10
1
write-only
P11
Input Change Interrupt Enable
11
1
write-only
P12
Input Change Interrupt Enable
12
1
write-only
P13
Input Change Interrupt Enable
13
1
write-only
P14
Input Change Interrupt Enable
14
1
write-only
P15
Input Change Interrupt Enable
15
1
write-only
P16
Input Change Interrupt Enable
16
1
write-only
P17
Input Change Interrupt Enable
17
1
write-only
P18
Input Change Interrupt Enable
18
1
write-only
P19
Input Change Interrupt Enable
19
1
write-only
P2
Input Change Interrupt Enable
2
1
write-only
P20
Input Change Interrupt Enable
20
1
write-only
P21
Input Change Interrupt Enable
21
1
write-only
P22
Input Change Interrupt Enable
22
1
write-only
P23
Input Change Interrupt Enable
23
1
write-only
P24
Input Change Interrupt Enable
24
1
write-only
P25
Input Change Interrupt Enable
25
1
write-only
P26
Input Change Interrupt Enable
26
1
write-only
P27
Input Change Interrupt Enable
27
1
write-only
P28
Input Change Interrupt Enable
28
1
write-only
P29
Input Change Interrupt Enable
29
1
write-only
P3
Input Change Interrupt Enable
3
1
write-only
P30
Input Change Interrupt Enable
30
1
write-only
P31
Input Change Interrupt Enable
31
1
write-only
P4
Input Change Interrupt Enable
4
1
write-only
P5
Input Change Interrupt Enable
5
1
write-only
P6
Input Change Interrupt Enable
6
1
write-only
P7
Input Change Interrupt Enable
7
1
write-only
P8
Input Change Interrupt Enable
8
1
write-only
P9
Input Change Interrupt Enable
9
1
write-only
IFDR
Glitch Input Filter Disable Register
0x24
32
write-only
n
0x0
0x0
P0
Input Filter Disable
0
1
write-only
P1
Input Filter Disable
1
1
write-only
P10
Input Filter Disable
10
1
write-only
P11
Input Filter Disable
11
1
write-only
P12
Input Filter Disable
12
1
write-only
P13
Input Filter Disable
13
1
write-only
P14
Input Filter Disable
14
1
write-only
P15
Input Filter Disable
15
1
write-only
P16
Input Filter Disable
16
1
write-only
P17
Input Filter Disable
17
1
write-only
P18
Input Filter Disable
18
1
write-only
P19
Input Filter Disable
19
1
write-only
P2
Input Filter Disable
2
1
write-only
P20
Input Filter Disable
20
1
write-only
P21
Input Filter Disable
21
1
write-only
P22
Input Filter Disable
22
1
write-only
P23
Input Filter Disable
23
1
write-only
P24
Input Filter Disable
24
1
write-only
P25
Input Filter Disable
25
1
write-only
P26
Input Filter Disable
26
1
write-only
P27
Input Filter Disable
27
1
write-only
P28
Input Filter Disable
28
1
write-only
P29
Input Filter Disable
29
1
write-only
P3
Input Filter Disable
3
1
write-only
P30
Input Filter Disable
30
1
write-only
P31
Input Filter Disable
31
1
write-only
P4
Input Filter Disable
4
1
write-only
P5
Input Filter Disable
5
1
write-only
P6
Input Filter Disable
6
1
write-only
P7
Input Filter Disable
7
1
write-only
P8
Input Filter Disable
8
1
write-only
P9
Input Filter Disable
9
1
write-only
IFER
Glitch Input Filter Enable Register
0x20
32
write-only
n
0x0
0x0
P0
Input Filter Enable
0
1
write-only
P1
Input Filter Enable
1
1
write-only
P10
Input Filter Enable
10
1
write-only
P11
Input Filter Enable
11
1
write-only
P12
Input Filter Enable
12
1
write-only
P13
Input Filter Enable
13
1
write-only
P14
Input Filter Enable
14
1
write-only
P15
Input Filter Enable
15
1
write-only
P16
Input Filter Enable
16
1
write-only
P17
Input Filter Enable
17
1
write-only
P18
Input Filter Enable
18
1
write-only
P19
Input Filter Enable
19
1
write-only
P2
Input Filter Enable
2
1
write-only
P20
Input Filter Enable
20
1
write-only
P21
Input Filter Enable
21
1
write-only
P22
Input Filter Enable
22
1
write-only
P23
Input Filter Enable
23
1
write-only
P24
Input Filter Enable
24
1
write-only
P25
Input Filter Enable
25
1
write-only
P26
Input Filter Enable
26
1
write-only
P27
Input Filter Enable
27
1
write-only
P28
Input Filter Enable
28
1
write-only
P29
Input Filter Enable
29
1
write-only
P3
Input Filter Enable
3
1
write-only
P30
Input Filter Enable
30
1
write-only
P31
Input Filter Enable
31
1
write-only
P4
Input Filter Enable
4
1
write-only
P5
Input Filter Enable
5
1
write-only
P6
Input Filter Enable
6
1
write-only
P7
Input Filter Enable
7
1
write-only
P8
Input Filter Enable
8
1
write-only
P9
Input Filter Enable
9
1
write-only
IFSCDR
Input Filter Slow Clock Disable Register
0x80
32
write-only
n
0x0
0x0
P0
Peripheral Clock Glitch Filtering Select
0
1
write-only
P1
Peripheral Clock Glitch Filtering Select
1
1
write-only
P10
Peripheral Clock Glitch Filtering Select
10
1
write-only
P11
Peripheral Clock Glitch Filtering Select
11
1
write-only
P12
Peripheral Clock Glitch Filtering Select
12
1
write-only
P13
Peripheral Clock Glitch Filtering Select
13
1
write-only
P14
Peripheral Clock Glitch Filtering Select
14
1
write-only
P15
Peripheral Clock Glitch Filtering Select
15
1
write-only
P16
Peripheral Clock Glitch Filtering Select
16
1
write-only
P17
Peripheral Clock Glitch Filtering Select
17
1
write-only
P18
Peripheral Clock Glitch Filtering Select
18
1
write-only
P19
Peripheral Clock Glitch Filtering Select
19
1
write-only
P2
Peripheral Clock Glitch Filtering Select
2
1
write-only
P20
Peripheral Clock Glitch Filtering Select
20
1
write-only
P21
Peripheral Clock Glitch Filtering Select
21
1
write-only
P22
Peripheral Clock Glitch Filtering Select
22
1
write-only
P23
Peripheral Clock Glitch Filtering Select
23
1
write-only
P24
Peripheral Clock Glitch Filtering Select
24
1
write-only
P25
Peripheral Clock Glitch Filtering Select
25
1
write-only
P26
Peripheral Clock Glitch Filtering Select
26
1
write-only
P27
Peripheral Clock Glitch Filtering Select
27
1
write-only
P28
Peripheral Clock Glitch Filtering Select
28
1
write-only
P29
Peripheral Clock Glitch Filtering Select
29
1
write-only
P3
Peripheral Clock Glitch Filtering Select
3
1
write-only
P30
Peripheral Clock Glitch Filtering Select
30
1
write-only
P31
Peripheral Clock Glitch Filtering Select
31
1
write-only
P4
Peripheral Clock Glitch Filtering Select
4
1
write-only
P5
Peripheral Clock Glitch Filtering Select
5
1
write-only
P6
Peripheral Clock Glitch Filtering Select
6
1
write-only
P7
Peripheral Clock Glitch Filtering Select
7
1
write-only
P8
Peripheral Clock Glitch Filtering Select
8
1
write-only
P9
Peripheral Clock Glitch Filtering Select
9
1
write-only
IFSCER
Input Filter Slow Clock Enable Register
0x84
32
write-only
n
0x0
0x0
P0
Slow Clock Debouncing Filtering Select
0
1
write-only
P1
Slow Clock Debouncing Filtering Select
1
1
write-only
P10
Slow Clock Debouncing Filtering Select
10
1
write-only
P11
Slow Clock Debouncing Filtering Select
11
1
write-only
P12
Slow Clock Debouncing Filtering Select
12
1
write-only
P13
Slow Clock Debouncing Filtering Select
13
1
write-only
P14
Slow Clock Debouncing Filtering Select
14
1
write-only
P15
Slow Clock Debouncing Filtering Select
15
1
write-only
P16
Slow Clock Debouncing Filtering Select
16
1
write-only
P17
Slow Clock Debouncing Filtering Select
17
1
write-only
P18
Slow Clock Debouncing Filtering Select
18
1
write-only
P19
Slow Clock Debouncing Filtering Select
19
1
write-only
P2
Slow Clock Debouncing Filtering Select
2
1
write-only
P20
Slow Clock Debouncing Filtering Select
20
1
write-only
P21
Slow Clock Debouncing Filtering Select
21
1
write-only
P22
Slow Clock Debouncing Filtering Select
22
1
write-only
P23
Slow Clock Debouncing Filtering Select
23
1
write-only
P24
Slow Clock Debouncing Filtering Select
24
1
write-only
P25
Slow Clock Debouncing Filtering Select
25
1
write-only
P26
Slow Clock Debouncing Filtering Select
26
1
write-only
P27
Slow Clock Debouncing Filtering Select
27
1
write-only
P28
Slow Clock Debouncing Filtering Select
28
1
write-only
P29
Slow Clock Debouncing Filtering Select
29
1
write-only
P3
Slow Clock Debouncing Filtering Select
3
1
write-only
P30
Slow Clock Debouncing Filtering Select
30
1
write-only
P31
Slow Clock Debouncing Filtering Select
31
1
write-only
P4
Slow Clock Debouncing Filtering Select
4
1
write-only
P5
Slow Clock Debouncing Filtering Select
5
1
write-only
P6
Slow Clock Debouncing Filtering Select
6
1
write-only
P7
Slow Clock Debouncing Filtering Select
7
1
write-only
P8
Slow Clock Debouncing Filtering Select
8
1
write-only
P9
Slow Clock Debouncing Filtering Select
9
1
write-only
IFSCSR
Input Filter Slow Clock Status Register
0x88
32
read-only
n
0x0
0x0
P0
Glitch or Debouncing Filter Selection Status
0
1
read-only
P1
Glitch or Debouncing Filter Selection Status
1
1
read-only
P10
Glitch or Debouncing Filter Selection Status
10
1
read-only
P11
Glitch or Debouncing Filter Selection Status
11
1
read-only
P12
Glitch or Debouncing Filter Selection Status
12
1
read-only
P13
Glitch or Debouncing Filter Selection Status
13
1
read-only
P14
Glitch or Debouncing Filter Selection Status
14
1
read-only
P15
Glitch or Debouncing Filter Selection Status
15
1
read-only
P16
Glitch or Debouncing Filter Selection Status
16
1
read-only
P17
Glitch or Debouncing Filter Selection Status
17
1
read-only
P18
Glitch or Debouncing Filter Selection Status
18
1
read-only
P19
Glitch or Debouncing Filter Selection Status
19
1
read-only
P2
Glitch or Debouncing Filter Selection Status
2
1
read-only
P20
Glitch or Debouncing Filter Selection Status
20
1
read-only
P21
Glitch or Debouncing Filter Selection Status
21
1
read-only
P22
Glitch or Debouncing Filter Selection Status
22
1
read-only
P23
Glitch or Debouncing Filter Selection Status
23
1
read-only
P24
Glitch or Debouncing Filter Selection Status
24
1
read-only
P25
Glitch or Debouncing Filter Selection Status
25
1
read-only
P26
Glitch or Debouncing Filter Selection Status
26
1
read-only
P27
Glitch or Debouncing Filter Selection Status
27
1
read-only
P28
Glitch or Debouncing Filter Selection Status
28
1
read-only
P29
Glitch or Debouncing Filter Selection Status
29
1
read-only
P3
Glitch or Debouncing Filter Selection Status
3
1
read-only
P30
Glitch or Debouncing Filter Selection Status
30
1
read-only
P31
Glitch or Debouncing Filter Selection Status
31
1
read-only
P4
Glitch or Debouncing Filter Selection Status
4
1
read-only
P5
Glitch or Debouncing Filter Selection Status
5
1
read-only
P6
Glitch or Debouncing Filter Selection Status
6
1
read-only
P7
Glitch or Debouncing Filter Selection Status
7
1
read-only
P8
Glitch or Debouncing Filter Selection Status
8
1
read-only
P9
Glitch or Debouncing Filter Selection Status
9
1
read-only
IFSR
Glitch Input Filter Status Register
0x28
32
read-only
n
0x0
0x0
P0
Input Filer Status
0
1
read-only
P1
Input Filer Status
1
1
read-only
P10
Input Filer Status
10
1
read-only
P11
Input Filer Status
11
1
read-only
P12
Input Filer Status
12
1
read-only
P13
Input Filer Status
13
1
read-only
P14
Input Filer Status
14
1
read-only
P15
Input Filer Status
15
1
read-only
P16
Input Filer Status
16
1
read-only
P17
Input Filer Status
17
1
read-only
P18
Input Filer Status
18
1
read-only
P19
Input Filer Status
19
1
read-only
P2
Input Filer Status
2
1
read-only
P20
Input Filer Status
20
1
read-only
P21
Input Filer Status
21
1
read-only
P22
Input Filer Status
22
1
read-only
P23
Input Filer Status
23
1
read-only
P24
Input Filer Status
24
1
read-only
P25
Input Filer Status
25
1
read-only
P26
Input Filer Status
26
1
read-only
P27
Input Filer Status
27
1
read-only
P28
Input Filer Status
28
1
read-only
P29
Input Filer Status
29
1
read-only
P3
Input Filer Status
3
1
read-only
P30
Input Filer Status
30
1
read-only
P31
Input Filer Status
31
1
read-only
P4
Input Filer Status
4
1
read-only
P5
Input Filer Status
5
1
read-only
P6
Input Filer Status
6
1
read-only
P7
Input Filer Status
7
1
read-only
P8
Input Filer Status
8
1
read-only
P9
Input Filer Status
9
1
read-only
IMR
Interrupt Mask Register
0x48
32
read-only
n
0x0
0x0
P0
Input Change Interrupt Mask
0
1
read-only
P1
Input Change Interrupt Mask
1
1
read-only
P10
Input Change Interrupt Mask
10
1
read-only
P11
Input Change Interrupt Mask
11
1
read-only
P12
Input Change Interrupt Mask
12
1
read-only
P13
Input Change Interrupt Mask
13
1
read-only
P14
Input Change Interrupt Mask
14
1
read-only
P15
Input Change Interrupt Mask
15
1
read-only
P16
Input Change Interrupt Mask
16
1
read-only
P17
Input Change Interrupt Mask
17
1
read-only
P18
Input Change Interrupt Mask
18
1
read-only
P19
Input Change Interrupt Mask
19
1
read-only
P2
Input Change Interrupt Mask
2
1
read-only
P20
Input Change Interrupt Mask
20
1
read-only
P21
Input Change Interrupt Mask
21
1
read-only
P22
Input Change Interrupt Mask
22
1
read-only
P23
Input Change Interrupt Mask
23
1
read-only
P24
Input Change Interrupt Mask
24
1
read-only
P25
Input Change Interrupt Mask
25
1
read-only
P26
Input Change Interrupt Mask
26
1
read-only
P27
Input Change Interrupt Mask
27
1
read-only
P28
Input Change Interrupt Mask
28
1
read-only
P29
Input Change Interrupt Mask
29
1
read-only
P3
Input Change Interrupt Mask
3
1
read-only
P30
Input Change Interrupt Mask
30
1
read-only
P31
Input Change Interrupt Mask
31
1
read-only
P4
Input Change Interrupt Mask
4
1
read-only
P5
Input Change Interrupt Mask
5
1
read-only
P6
Input Change Interrupt Mask
6
1
read-only
P7
Input Change Interrupt Mask
7
1
read-only
P8
Input Change Interrupt Mask
8
1
read-only
P9
Input Change Interrupt Mask
9
1
read-only
ISR
Interrupt Status Register
0x4C
32
read-only
n
0x0
0x0
P0
Input Change Interrupt Status
0
1
read-only
P1
Input Change Interrupt Status
1
1
read-only
P10
Input Change Interrupt Status
10
1
read-only
P11
Input Change Interrupt Status
11
1
read-only
P12
Input Change Interrupt Status
12
1
read-only
P13
Input Change Interrupt Status
13
1
read-only
P14
Input Change Interrupt Status
14
1
read-only
P15
Input Change Interrupt Status
15
1
read-only
P16
Input Change Interrupt Status
16
1
read-only
P17
Input Change Interrupt Status
17
1
read-only
P18
Input Change Interrupt Status
18
1
read-only
P19
Input Change Interrupt Status
19
1
read-only
P2
Input Change Interrupt Status
2
1
read-only
P20
Input Change Interrupt Status
20
1
read-only
P21
Input Change Interrupt Status
21
1
read-only
P22
Input Change Interrupt Status
22
1
read-only
P23
Input Change Interrupt Status
23
1
read-only
P24
Input Change Interrupt Status
24
1
read-only
P25
Input Change Interrupt Status
25
1
read-only
P26
Input Change Interrupt Status
26
1
read-only
P27
Input Change Interrupt Status
27
1
read-only
P28
Input Change Interrupt Status
28
1
read-only
P29
Input Change Interrupt Status
29
1
read-only
P3
Input Change Interrupt Status
3
1
read-only
P30
Input Change Interrupt Status
30
1
read-only
P31
Input Change Interrupt Status
31
1
read-only
P4
Input Change Interrupt Status
4
1
read-only
P5
Input Change Interrupt Status
5
1
read-only
P6
Input Change Interrupt Status
6
1
read-only
P7
Input Change Interrupt Status
7
1
read-only
P8
Input Change Interrupt Status
8
1
read-only
P9
Input Change Interrupt Status
9
1
read-only
LSR
Level Select Register
0xC4
32
write-only
n
0x0
0x0
P0
Level Interrupt Selection
0
1
write-only
P1
Level Interrupt Selection
1
1
write-only
P10
Level Interrupt Selection
10
1
write-only
P11
Level Interrupt Selection
11
1
write-only
P12
Level Interrupt Selection
12
1
write-only
P13
Level Interrupt Selection
13
1
write-only
P14
Level Interrupt Selection
14
1
write-only
P15
Level Interrupt Selection
15
1
write-only
P16
Level Interrupt Selection
16
1
write-only
P17
Level Interrupt Selection
17
1
write-only
P18
Level Interrupt Selection
18
1
write-only
P19
Level Interrupt Selection
19
1
write-only
P2
Level Interrupt Selection
2
1
write-only
P20
Level Interrupt Selection
20
1
write-only
P21
Level Interrupt Selection
21
1
write-only
P22
Level Interrupt Selection
22
1
write-only
P23
Level Interrupt Selection
23
1
write-only
P24
Level Interrupt Selection
24
1
write-only
P25
Level Interrupt Selection
25
1
write-only
P26
Level Interrupt Selection
26
1
write-only
P27
Level Interrupt Selection
27
1
write-only
P28
Level Interrupt Selection
28
1
write-only
P29
Level Interrupt Selection
29
1
write-only
P3
Level Interrupt Selection
3
1
write-only
P30
Level Interrupt Selection
30
1
write-only
P31
Level Interrupt Selection
31
1
write-only
P4
Level Interrupt Selection
4
1
write-only
P5
Level Interrupt Selection
5
1
write-only
P6
Level Interrupt Selection
6
1
write-only
P7
Level Interrupt Selection
7
1
write-only
P8
Level Interrupt Selection
8
1
write-only
P9
Level Interrupt Selection
9
1
write-only
MDDR
Multi-driver Disable Register
0x54
32
write-only
n
0x0
0x0
P0
Multi-drive Disable
0
1
write-only
P1
Multi-drive Disable
1
1
write-only
P10
Multi-drive Disable
10
1
write-only
P11
Multi-drive Disable
11
1
write-only
P12
Multi-drive Disable
12
1
write-only
P13
Multi-drive Disable
13
1
write-only
P14
Multi-drive Disable
14
1
write-only
P15
Multi-drive Disable
15
1
write-only
P16
Multi-drive Disable
16
1
write-only
P17
Multi-drive Disable
17
1
write-only
P18
Multi-drive Disable
18
1
write-only
P19
Multi-drive Disable
19
1
write-only
P2
Multi-drive Disable
2
1
write-only
P20
Multi-drive Disable
20
1
write-only
P21
Multi-drive Disable
21
1
write-only
P22
Multi-drive Disable
22
1
write-only
P23
Multi-drive Disable
23
1
write-only
P24
Multi-drive Disable
24
1
write-only
P25
Multi-drive Disable
25
1
write-only
P26
Multi-drive Disable
26
1
write-only
P27
Multi-drive Disable
27
1
write-only
P28
Multi-drive Disable
28
1
write-only
P29
Multi-drive Disable
29
1
write-only
P3
Multi-drive Disable
3
1
write-only
P30
Multi-drive Disable
30
1
write-only
P31
Multi-drive Disable
31
1
write-only
P4
Multi-drive Disable
4
1
write-only
P5
Multi-drive Disable
5
1
write-only
P6
Multi-drive Disable
6
1
write-only
P7
Multi-drive Disable
7
1
write-only
P8
Multi-drive Disable
8
1
write-only
P9
Multi-drive Disable
9
1
write-only
MDER
Multi-driver Enable Register
0x50
32
write-only
n
0x0
0x0
P0
Multi-drive Enable
0
1
write-only
P1
Multi-drive Enable
1
1
write-only
P10
Multi-drive Enable
10
1
write-only
P11
Multi-drive Enable
11
1
write-only
P12
Multi-drive Enable
12
1
write-only
P13
Multi-drive Enable
13
1
write-only
P14
Multi-drive Enable
14
1
write-only
P15
Multi-drive Enable
15
1
write-only
P16
Multi-drive Enable
16
1
write-only
P17
Multi-drive Enable
17
1
write-only
P18
Multi-drive Enable
18
1
write-only
P19
Multi-drive Enable
19
1
write-only
P2
Multi-drive Enable
2
1
write-only
P20
Multi-drive Enable
20
1
write-only
P21
Multi-drive Enable
21
1
write-only
P22
Multi-drive Enable
22
1
write-only
P23
Multi-drive Enable
23
1
write-only
P24
Multi-drive Enable
24
1
write-only
P25
Multi-drive Enable
25
1
write-only
P26
Multi-drive Enable
26
1
write-only
P27
Multi-drive Enable
27
1
write-only
P28
Multi-drive Enable
28
1
write-only
P29
Multi-drive Enable
29
1
write-only
P3
Multi-drive Enable
3
1
write-only
P30
Multi-drive Enable
30
1
write-only
P31
Multi-drive Enable
31
1
write-only
P4
Multi-drive Enable
4
1
write-only
P5
Multi-drive Enable
5
1
write-only
P6
Multi-drive Enable
6
1
write-only
P7
Multi-drive Enable
7
1
write-only
P8
Multi-drive Enable
8
1
write-only
P9
Multi-drive Enable
9
1
write-only
MDSR
Multi-driver Status Register
0x58
32
read-only
n
0x0
0x0
P0
Multi-drive Status
0
1
read-only
P1
Multi-drive Status
1
1
read-only
P10
Multi-drive Status
10
1
read-only
P11
Multi-drive Status
11
1
read-only
P12
Multi-drive Status
12
1
read-only
P13
Multi-drive Status
13
1
read-only
P14
Multi-drive Status
14
1
read-only
P15
Multi-drive Status
15
1
read-only
P16
Multi-drive Status
16
1
read-only
P17
Multi-drive Status
17
1
read-only
P18
Multi-drive Status
18
1
read-only
P19
Multi-drive Status
19
1
read-only
P2
Multi-drive Status
2
1
read-only
P20
Multi-drive Status
20
1
read-only
P21
Multi-drive Status
21
1
read-only
P22
Multi-drive Status
22
1
read-only
P23
Multi-drive Status
23
1
read-only
P24
Multi-drive Status
24
1
read-only
P25
Multi-drive Status
25
1
read-only
P26
Multi-drive Status
26
1
read-only
P27
Multi-drive Status
27
1
read-only
P28
Multi-drive Status
28
1
read-only
P29
Multi-drive Status
29
1
read-only
P3
Multi-drive Status
3
1
read-only
P30
Multi-drive Status
30
1
read-only
P31
Multi-drive Status
31
1
read-only
P4
Multi-drive Status
4
1
read-only
P5
Multi-drive Status
5
1
read-only
P6
Multi-drive Status
6
1
read-only
P7
Multi-drive Status
7
1
read-only
P8
Multi-drive Status
8
1
read-only
P9
Multi-drive Status
9
1
read-only
ODR
Output Disable Register
0x14
32
write-only
n
0x0
0x0
P0
Output Disable
0
1
write-only
P1
Output Disable
1
1
write-only
P10
Output Disable
10
1
write-only
P11
Output Disable
11
1
write-only
P12
Output Disable
12
1
write-only
P13
Output Disable
13
1
write-only
P14
Output Disable
14
1
write-only
P15
Output Disable
15
1
write-only
P16
Output Disable
16
1
write-only
P17
Output Disable
17
1
write-only
P18
Output Disable
18
1
write-only
P19
Output Disable
19
1
write-only
P2
Output Disable
2
1
write-only
P20
Output Disable
20
1
write-only
P21
Output Disable
21
1
write-only
P22
Output Disable
22
1
write-only
P23
Output Disable
23
1
write-only
P24
Output Disable
24
1
write-only
P25
Output Disable
25
1
write-only
P26
Output Disable
26
1
write-only
P27
Output Disable
27
1
write-only
P28
Output Disable
28
1
write-only
P29
Output Disable
29
1
write-only
P3
Output Disable
3
1
write-only
P30
Output Disable
30
1
write-only
P31
Output Disable
31
1
write-only
P4
Output Disable
4
1
write-only
P5
Output Disable
5
1
write-only
P6
Output Disable
6
1
write-only
P7
Output Disable
7
1
write-only
P8
Output Disable
8
1
write-only
P9
Output Disable
9
1
write-only
ODSR
Output Data Status Register
0x38
32
read-write
n
0x0
0x0
P0
Output Data Status
0
1
read-write
P1
Output Data Status
1
1
read-write
P10
Output Data Status
10
1
read-write
P11
Output Data Status
11
1
read-write
P12
Output Data Status
12
1
read-write
P13
Output Data Status
13
1
read-write
P14
Output Data Status
14
1
read-write
P15
Output Data Status
15
1
read-write
P16
Output Data Status
16
1
read-write
P17
Output Data Status
17
1
read-write
P18
Output Data Status
18
1
read-write
P19
Output Data Status
19
1
read-write
P2
Output Data Status
2
1
read-write
P20
Output Data Status
20
1
read-write
P21
Output Data Status
21
1
read-write
P22
Output Data Status
22
1
read-write
P23
Output Data Status
23
1
read-write
P24
Output Data Status
24
1
read-write
P25
Output Data Status
25
1
read-write
P26
Output Data Status
26
1
read-write
P27
Output Data Status
27
1
read-write
P28
Output Data Status
28
1
read-write
P29
Output Data Status
29
1
read-write
P3
Output Data Status
3
1
read-write
P30
Output Data Status
30
1
read-write
P31
Output Data Status
31
1
read-write
P4
Output Data Status
4
1
read-write
P5
Output Data Status
5
1
read-write
P6
Output Data Status
6
1
read-write
P7
Output Data Status
7
1
read-write
P8
Output Data Status
8
1
read-write
P9
Output Data Status
9
1
read-write
OER
Output Enable Register
0x10
32
write-only
n
0x0
0x0
P0
Output Enable
0
1
write-only
P1
Output Enable
1
1
write-only
P10
Output Enable
10
1
write-only
P11
Output Enable
11
1
write-only
P12
Output Enable
12
1
write-only
P13
Output Enable
13
1
write-only
P14
Output Enable
14
1
write-only
P15
Output Enable
15
1
write-only
P16
Output Enable
16
1
write-only
P17
Output Enable
17
1
write-only
P18
Output Enable
18
1
write-only
P19
Output Enable
19
1
write-only
P2
Output Enable
2
1
write-only
P20
Output Enable
20
1
write-only
P21
Output Enable
21
1
write-only
P22
Output Enable
22
1
write-only
P23
Output Enable
23
1
write-only
P24
Output Enable
24
1
write-only
P25
Output Enable
25
1
write-only
P26
Output Enable
26
1
write-only
P27
Output Enable
27
1
write-only
P28
Output Enable
28
1
write-only
P29
Output Enable
29
1
write-only
P3
Output Enable
3
1
write-only
P30
Output Enable
30
1
write-only
P31
Output Enable
31
1
write-only
P4
Output Enable
4
1
write-only
P5
Output Enable
5
1
write-only
P6
Output Enable
6
1
write-only
P7
Output Enable
7
1
write-only
P8
Output Enable
8
1
write-only
P9
Output Enable
9
1
write-only
OSR
Output Status Register
0x18
32
read-only
n
0x0
0x0
P0
Output Status
0
1
read-only
P1
Output Status
1
1
read-only
P10
Output Status
10
1
read-only
P11
Output Status
11
1
read-only
P12
Output Status
12
1
read-only
P13
Output Status
13
1
read-only
P14
Output Status
14
1
read-only
P15
Output Status
15
1
read-only
P16
Output Status
16
1
read-only
P17
Output Status
17
1
read-only
P18
Output Status
18
1
read-only
P19
Output Status
19
1
read-only
P2
Output Status
2
1
read-only
P20
Output Status
20
1
read-only
P21
Output Status
21
1
read-only
P22
Output Status
22
1
read-only
P23
Output Status
23
1
read-only
P24
Output Status
24
1
read-only
P25
Output Status
25
1
read-only
P26
Output Status
26
1
read-only
P27
Output Status
27
1
read-only
P28
Output Status
28
1
read-only
P29
Output Status
29
1
read-only
P3
Output Status
3
1
read-only
P30
Output Status
30
1
read-only
P31
Output Status
31
1
read-only
P4
Output Status
4
1
read-only
P5
Output Status
5
1
read-only
P6
Output Status
6
1
read-only
P7
Output Status
7
1
read-only
P8
Output Status
8
1
read-only
P9
Output Status
9
1
read-only
OWDR
Output Write Disable
0xA4
32
write-only
n
0x0
0x0
P0
Output Write Disable
0
1
write-only
P1
Output Write Disable
1
1
write-only
P10
Output Write Disable
10
1
write-only
P11
Output Write Disable
11
1
write-only
P12
Output Write Disable
12
1
write-only
P13
Output Write Disable
13
1
write-only
P14
Output Write Disable
14
1
write-only
P15
Output Write Disable
15
1
write-only
P16
Output Write Disable
16
1
write-only
P17
Output Write Disable
17
1
write-only
P18
Output Write Disable
18
1
write-only
P19
Output Write Disable
19
1
write-only
P2
Output Write Disable
2
1
write-only
P20
Output Write Disable
20
1
write-only
P21
Output Write Disable
21
1
write-only
P22
Output Write Disable
22
1
write-only
P23
Output Write Disable
23
1
write-only
P24
Output Write Disable
24
1
write-only
P25
Output Write Disable
25
1
write-only
P26
Output Write Disable
26
1
write-only
P27
Output Write Disable
27
1
write-only
P28
Output Write Disable
28
1
write-only
P29
Output Write Disable
29
1
write-only
P3
Output Write Disable
3
1
write-only
P30
Output Write Disable
30
1
write-only
P31
Output Write Disable
31
1
write-only
P4
Output Write Disable
4
1
write-only
P5
Output Write Disable
5
1
write-only
P6
Output Write Disable
6
1
write-only
P7
Output Write Disable
7
1
write-only
P8
Output Write Disable
8
1
write-only
P9
Output Write Disable
9
1
write-only
OWER
Output Write Enable
0xA0
32
write-only
n
0x0
0x0
P0
Output Write Enable
0
1
write-only
P1
Output Write Enable
1
1
write-only
P10
Output Write Enable
10
1
write-only
P11
Output Write Enable
11
1
write-only
P12
Output Write Enable
12
1
write-only
P13
Output Write Enable
13
1
write-only
P14
Output Write Enable
14
1
write-only
P15
Output Write Enable
15
1
write-only
P16
Output Write Enable
16
1
write-only
P17
Output Write Enable
17
1
write-only
P18
Output Write Enable
18
1
write-only
P19
Output Write Enable
19
1
write-only
P2
Output Write Enable
2
1
write-only
P20
Output Write Enable
20
1
write-only
P21
Output Write Enable
21
1
write-only
P22
Output Write Enable
22
1
write-only
P23
Output Write Enable
23
1
write-only
P24
Output Write Enable
24
1
write-only
P25
Output Write Enable
25
1
write-only
P26
Output Write Enable
26
1
write-only
P27
Output Write Enable
27
1
write-only
P28
Output Write Enable
28
1
write-only
P29
Output Write Enable
29
1
write-only
P3
Output Write Enable
3
1
write-only
P30
Output Write Enable
30
1
write-only
P31
Output Write Enable
31
1
write-only
P4
Output Write Enable
4
1
write-only
P5
Output Write Enable
5
1
write-only
P6
Output Write Enable
6
1
write-only
P7
Output Write Enable
7
1
write-only
P8
Output Write Enable
8
1
write-only
P9
Output Write Enable
9
1
write-only
OWSR
Output Write Status Register
0xA8
32
read-only
n
0x0
0x0
P0
Output Write Status
0
1
read-only
P1
Output Write Status
1
1
read-only
P10
Output Write Status
10
1
read-only
P11
Output Write Status
11
1
read-only
P12
Output Write Status
12
1
read-only
P13
Output Write Status
13
1
read-only
P14
Output Write Status
14
1
read-only
P15
Output Write Status
15
1
read-only
P16
Output Write Status
16
1
read-only
P17
Output Write Status
17
1
read-only
P18
Output Write Status
18
1
read-only
P19
Output Write Status
19
1
read-only
P2
Output Write Status
2
1
read-only
P20
Output Write Status
20
1
read-only
P21
Output Write Status
21
1
read-only
P22
Output Write Status
22
1
read-only
P23
Output Write Status
23
1
read-only
P24
Output Write Status
24
1
read-only
P25
Output Write Status
25
1
read-only
P26
Output Write Status
26
1
read-only
P27
Output Write Status
27
1
read-only
P28
Output Write Status
28
1
read-only
P29
Output Write Status
29
1
read-only
P3
Output Write Status
3
1
read-only
P30
Output Write Status
30
1
read-only
P31
Output Write Status
31
1
read-only
P4
Output Write Status
4
1
read-only
P5
Output Write Status
5
1
read-only
P6
Output Write Status
6
1
read-only
P7
Output Write Status
7
1
read-only
P8
Output Write Status
8
1
read-only
P9
Output Write Status
9
1
read-only
PDR
PIO Disable Register
0x4
32
write-only
n
0x0
0x0
P0
PIO Disable
0
1
write-only
P1
PIO Disable
1
1
write-only
P10
PIO Disable
10
1
write-only
P11
PIO Disable
11
1
write-only
P12
PIO Disable
12
1
write-only
P13
PIO Disable
13
1
write-only
P14
PIO Disable
14
1
write-only
P15
PIO Disable
15
1
write-only
P16
PIO Disable
16
1
write-only
P17
PIO Disable
17
1
write-only
P18
PIO Disable
18
1
write-only
P19
PIO Disable
19
1
write-only
P2
PIO Disable
2
1
write-only
P20
PIO Disable
20
1
write-only
P21
PIO Disable
21
1
write-only
P22
PIO Disable
22
1
write-only
P23
PIO Disable
23
1
write-only
P24
PIO Disable
24
1
write-only
P25
PIO Disable
25
1
write-only
P26
PIO Disable
26
1
write-only
P27
PIO Disable
27
1
write-only
P28
PIO Disable
28
1
write-only
P29
PIO Disable
29
1
write-only
P3
PIO Disable
3
1
write-only
P30
PIO Disable
30
1
write-only
P31
PIO Disable
31
1
write-only
P4
PIO Disable
4
1
write-only
P5
PIO Disable
5
1
write-only
P6
PIO Disable
6
1
write-only
P7
PIO Disable
7
1
write-only
P8
PIO Disable
8
1
write-only
P9
PIO Disable
9
1
write-only
PDSR
Pin Data Status Register
0x3C
32
read-only
n
0x0
0x0
P0
Output Data Status
0
1
read-only
P1
Output Data Status
1
1
read-only
P10
Output Data Status
10
1
read-only
P11
Output Data Status
11
1
read-only
P12
Output Data Status
12
1
read-only
P13
Output Data Status
13
1
read-only
P14
Output Data Status
14
1
read-only
P15
Output Data Status
15
1
read-only
P16
Output Data Status
16
1
read-only
P17
Output Data Status
17
1
read-only
P18
Output Data Status
18
1
read-only
P19
Output Data Status
19
1
read-only
P2
Output Data Status
2
1
read-only
P20
Output Data Status
20
1
read-only
P21
Output Data Status
21
1
read-only
P22
Output Data Status
22
1
read-only
P23
Output Data Status
23
1
read-only
P24
Output Data Status
24
1
read-only
P25
Output Data Status
25
1
read-only
P26
Output Data Status
26
1
read-only
P27
Output Data Status
27
1
read-only
P28
Output Data Status
28
1
read-only
P29
Output Data Status
29
1
read-only
P3
Output Data Status
3
1
read-only
P30
Output Data Status
30
1
read-only
P31
Output Data Status
31
1
read-only
P4
Output Data Status
4
1
read-only
P5
Output Data Status
5
1
read-only
P6
Output Data Status
6
1
read-only
P7
Output Data Status
7
1
read-only
P8
Output Data Status
8
1
read-only
P9
Output Data Status
9
1
read-only
PER
PIO Enable Register
0x0
32
write-only
n
0x0
0x0
P0
PIO Enable
0
1
write-only
P1
PIO Enable
1
1
write-only
P10
PIO Enable
10
1
write-only
P11
PIO Enable
11
1
write-only
P12
PIO Enable
12
1
write-only
P13
PIO Enable
13
1
write-only
P14
PIO Enable
14
1
write-only
P15
PIO Enable
15
1
write-only
P16
PIO Enable
16
1
write-only
P17
PIO Enable
17
1
write-only
P18
PIO Enable
18
1
write-only
P19
PIO Enable
19
1
write-only
P2
PIO Enable
2
1
write-only
P20
PIO Enable
20
1
write-only
P21
PIO Enable
21
1
write-only
P22
PIO Enable
22
1
write-only
P23
PIO Enable
23
1
write-only
P24
PIO Enable
24
1
write-only
P25
PIO Enable
25
1
write-only
P26
PIO Enable
26
1
write-only
P27
PIO Enable
27
1
write-only
P28
PIO Enable
28
1
write-only
P29
PIO Enable
29
1
write-only
P3
PIO Enable
3
1
write-only
P30
PIO Enable
30
1
write-only
P31
PIO Enable
31
1
write-only
P4
PIO Enable
4
1
write-only
P5
PIO Enable
5
1
write-only
P6
PIO Enable
6
1
write-only
P7
PIO Enable
7
1
write-only
P8
PIO Enable
8
1
write-only
P9
PIO Enable
9
1
write-only
PPDDR
Pad Pull-down Disable Register
0x90
32
write-only
n
0x0
0x0
P0
Pull-Down Disable
0
1
write-only
P1
Pull-Down Disable
1
1
write-only
P10
Pull-Down Disable
10
1
write-only
P11
Pull-Down Disable
11
1
write-only
P12
Pull-Down Disable
12
1
write-only
P13
Pull-Down Disable
13
1
write-only
P14
Pull-Down Disable
14
1
write-only
P15
Pull-Down Disable
15
1
write-only
P16
Pull-Down Disable
16
1
write-only
P17
Pull-Down Disable
17
1
write-only
P18
Pull-Down Disable
18
1
write-only
P19
Pull-Down Disable
19
1
write-only
P2
Pull-Down Disable
2
1
write-only
P20
Pull-Down Disable
20
1
write-only
P21
Pull-Down Disable
21
1
write-only
P22
Pull-Down Disable
22
1
write-only
P23
Pull-Down Disable
23
1
write-only
P24
Pull-Down Disable
24
1
write-only
P25
Pull-Down Disable
25
1
write-only
P26
Pull-Down Disable
26
1
write-only
P27
Pull-Down Disable
27
1
write-only
P28
Pull-Down Disable
28
1
write-only
P29
Pull-Down Disable
29
1
write-only
P3
Pull-Down Disable
3
1
write-only
P30
Pull-Down Disable
30
1
write-only
P31
Pull-Down Disable
31
1
write-only
P4
Pull-Down Disable
4
1
write-only
P5
Pull-Down Disable
5
1
write-only
P6
Pull-Down Disable
6
1
write-only
P7
Pull-Down Disable
7
1
write-only
P8
Pull-Down Disable
8
1
write-only
P9
Pull-Down Disable
9
1
write-only
PPDER
Pad Pull-down Enable Register
0x94
32
write-only
n
0x0
0x0
P0
Pull-Down Enable
0
1
write-only
P1
Pull-Down Enable
1
1
write-only
P10
Pull-Down Enable
10
1
write-only
P11
Pull-Down Enable
11
1
write-only
P12
Pull-Down Enable
12
1
write-only
P13
Pull-Down Enable
13
1
write-only
P14
Pull-Down Enable
14
1
write-only
P15
Pull-Down Enable
15
1
write-only
P16
Pull-Down Enable
16
1
write-only
P17
Pull-Down Enable
17
1
write-only
P18
Pull-Down Enable
18
1
write-only
P19
Pull-Down Enable
19
1
write-only
P2
Pull-Down Enable
2
1
write-only
P20
Pull-Down Enable
20
1
write-only
P21
Pull-Down Enable
21
1
write-only
P22
Pull-Down Enable
22
1
write-only
P23
Pull-Down Enable
23
1
write-only
P24
Pull-Down Enable
24
1
write-only
P25
Pull-Down Enable
25
1
write-only
P26
Pull-Down Enable
26
1
write-only
P27
Pull-Down Enable
27
1
write-only
P28
Pull-Down Enable
28
1
write-only
P29
Pull-Down Enable
29
1
write-only
P3
Pull-Down Enable
3
1
write-only
P30
Pull-Down Enable
30
1
write-only
P31
Pull-Down Enable
31
1
write-only
P4
Pull-Down Enable
4
1
write-only
P5
Pull-Down Enable
5
1
write-only
P6
Pull-Down Enable
6
1
write-only
P7
Pull-Down Enable
7
1
write-only
P8
Pull-Down Enable
8
1
write-only
P9
Pull-Down Enable
9
1
write-only
PPDSR
Pad Pull-down Status Register
0x98
32
read-only
n
0x0
0x0
P0
Pull-Down Status
0
1
read-only
P1
Pull-Down Status
1
1
read-only
P10
Pull-Down Status
10
1
read-only
P11
Pull-Down Status
11
1
read-only
P12
Pull-Down Status
12
1
read-only
P13
Pull-Down Status
13
1
read-only
P14
Pull-Down Status
14
1
read-only
P15
Pull-Down Status
15
1
read-only
P16
Pull-Down Status
16
1
read-only
P17
Pull-Down Status
17
1
read-only
P18
Pull-Down Status
18
1
read-only
P19
Pull-Down Status
19
1
read-only
P2
Pull-Down Status
2
1
read-only
P20
Pull-Down Status
20
1
read-only
P21
Pull-Down Status
21
1
read-only
P22
Pull-Down Status
22
1
read-only
P23
Pull-Down Status
23
1
read-only
P24
Pull-Down Status
24
1
read-only
P25
Pull-Down Status
25
1
read-only
P26
Pull-Down Status
26
1
read-only
P27
Pull-Down Status
27
1
read-only
P28
Pull-Down Status
28
1
read-only
P29
Pull-Down Status
29
1
read-only
P3
Pull-Down Status
3
1
read-only
P30
Pull-Down Status
30
1
read-only
P31
Pull-Down Status
31
1
read-only
P4
Pull-Down Status
4
1
read-only
P5
Pull-Down Status
5
1
read-only
P6
Pull-Down Status
6
1
read-only
P7
Pull-Down Status
7
1
read-only
P8
Pull-Down Status
8
1
read-only
P9
Pull-Down Status
9
1
read-only
PSR
PIO Status Register
0x8
32
read-only
n
0x0
0x0
P0
PIO Status
0
1
read-only
P1
PIO Status
1
1
read-only
P10
PIO Status
10
1
read-only
P11
PIO Status
11
1
read-only
P12
PIO Status
12
1
read-only
P13
PIO Status
13
1
read-only
P14
PIO Status
14
1
read-only
P15
PIO Status
15
1
read-only
P16
PIO Status
16
1
read-only
P17
PIO Status
17
1
read-only
P18
PIO Status
18
1
read-only
P19
PIO Status
19
1
read-only
P2
PIO Status
2
1
read-only
P20
PIO Status
20
1
read-only
P21
PIO Status
21
1
read-only
P22
PIO Status
22
1
read-only
P23
PIO Status
23
1
read-only
P24
PIO Status
24
1
read-only
P25
PIO Status
25
1
read-only
P26
PIO Status
26
1
read-only
P27
PIO Status
27
1
read-only
P28
PIO Status
28
1
read-only
P29
PIO Status
29
1
read-only
P3
PIO Status
3
1
read-only
P30
PIO Status
30
1
read-only
P31
PIO Status
31
1
read-only
P4
PIO Status
4
1
read-only
P5
PIO Status
5
1
read-only
P6
PIO Status
6
1
read-only
P7
PIO Status
7
1
read-only
P8
PIO Status
8
1
read-only
P9
PIO Status
9
1
read-only
PUDR
Pull-up Disable Register
0x60
32
write-only
n
0x0
0x0
P0
Pull-Up Disable
0
1
write-only
P1
Pull-Up Disable
1
1
write-only
P10
Pull-Up Disable
10
1
write-only
P11
Pull-Up Disable
11
1
write-only
P12
Pull-Up Disable
12
1
write-only
P13
Pull-Up Disable
13
1
write-only
P14
Pull-Up Disable
14
1
write-only
P15
Pull-Up Disable
15
1
write-only
P16
Pull-Up Disable
16
1
write-only
P17
Pull-Up Disable
17
1
write-only
P18
Pull-Up Disable
18
1
write-only
P19
Pull-Up Disable
19
1
write-only
P2
Pull-Up Disable
2
1
write-only
P20
Pull-Up Disable
20
1
write-only
P21
Pull-Up Disable
21
1
write-only
P22
Pull-Up Disable
22
1
write-only
P23
Pull-Up Disable
23
1
write-only
P24
Pull-Up Disable
24
1
write-only
P25
Pull-Up Disable
25
1
write-only
P26
Pull-Up Disable
26
1
write-only
P27
Pull-Up Disable
27
1
write-only
P28
Pull-Up Disable
28
1
write-only
P29
Pull-Up Disable
29
1
write-only
P3
Pull-Up Disable
3
1
write-only
P30
Pull-Up Disable
30
1
write-only
P31
Pull-Up Disable
31
1
write-only
P4
Pull-Up Disable
4
1
write-only
P5
Pull-Up Disable
5
1
write-only
P6
Pull-Up Disable
6
1
write-only
P7
Pull-Up Disable
7
1
write-only
P8
Pull-Up Disable
8
1
write-only
P9
Pull-Up Disable
9
1
write-only
PUER
Pull-up Enable Register
0x64
32
write-only
n
0x0
0x0
P0
Pull-Up Enable
0
1
write-only
P1
Pull-Up Enable
1
1
write-only
P10
Pull-Up Enable
10
1
write-only
P11
Pull-Up Enable
11
1
write-only
P12
Pull-Up Enable
12
1
write-only
P13
Pull-Up Enable
13
1
write-only
P14
Pull-Up Enable
14
1
write-only
P15
Pull-Up Enable
15
1
write-only
P16
Pull-Up Enable
16
1
write-only
P17
Pull-Up Enable
17
1
write-only
P18
Pull-Up Enable
18
1
write-only
P19
Pull-Up Enable
19
1
write-only
P2
Pull-Up Enable
2
1
write-only
P20
Pull-Up Enable
20
1
write-only
P21
Pull-Up Enable
21
1
write-only
P22
Pull-Up Enable
22
1
write-only
P23
Pull-Up Enable
23
1
write-only
P24
Pull-Up Enable
24
1
write-only
P25
Pull-Up Enable
25
1
write-only
P26
Pull-Up Enable
26
1
write-only
P27
Pull-Up Enable
27
1
write-only
P28
Pull-Up Enable
28
1
write-only
P29
Pull-Up Enable
29
1
write-only
P3
Pull-Up Enable
3
1
write-only
P30
Pull-Up Enable
30
1
write-only
P31
Pull-Up Enable
31
1
write-only
P4
Pull-Up Enable
4
1
write-only
P5
Pull-Up Enable
5
1
write-only
P6
Pull-Up Enable
6
1
write-only
P7
Pull-Up Enable
7
1
write-only
P8
Pull-Up Enable
8
1
write-only
P9
Pull-Up Enable
9
1
write-only
PUSR
Pad Pull-up Status Register
0x68
32
read-only
n
0x0
0x0
P0
Pull-Up Status
0
1
read-only
P1
Pull-Up Status
1
1
read-only
P10
Pull-Up Status
10
1
read-only
P11
Pull-Up Status
11
1
read-only
P12
Pull-Up Status
12
1
read-only
P13
Pull-Up Status
13
1
read-only
P14
Pull-Up Status
14
1
read-only
P15
Pull-Up Status
15
1
read-only
P16
Pull-Up Status
16
1
read-only
P17
Pull-Up Status
17
1
read-only
P18
Pull-Up Status
18
1
read-only
P19
Pull-Up Status
19
1
read-only
P2
Pull-Up Status
2
1
read-only
P20
Pull-Up Status
20
1
read-only
P21
Pull-Up Status
21
1
read-only
P22
Pull-Up Status
22
1
read-only
P23
Pull-Up Status
23
1
read-only
P24
Pull-Up Status
24
1
read-only
P25
Pull-Up Status
25
1
read-only
P26
Pull-Up Status
26
1
read-only
P27
Pull-Up Status
27
1
read-only
P28
Pull-Up Status
28
1
read-only
P29
Pull-Up Status
29
1
read-only
P3
Pull-Up Status
3
1
read-only
P30
Pull-Up Status
30
1
read-only
P31
Pull-Up Status
31
1
read-only
P4
Pull-Up Status
4
1
read-only
P5
Pull-Up Status
5
1
read-only
P6
Pull-Up Status
6
1
read-only
P7
Pull-Up Status
7
1
read-only
P8
Pull-Up Status
8
1
read-only
P9
Pull-Up Status
9
1
read-only
REHLSR
Rising Edge/High-Level Select Register
0xD4
32
write-only
n
0x0
0x0
P0
Rising Edge/High-Level Interrupt Selection
0
1
write-only
P1
Rising Edge/High-Level Interrupt Selection
1
1
write-only
P10
Rising Edge/High-Level Interrupt Selection
10
1
write-only
P11
Rising Edge/High-Level Interrupt Selection
11
1
write-only
P12
Rising Edge/High-Level Interrupt Selection
12
1
write-only
P13
Rising Edge/High-Level Interrupt Selection
13
1
write-only
P14
Rising Edge/High-Level Interrupt Selection
14
1
write-only
P15
Rising Edge/High-Level Interrupt Selection
15
1
write-only
P16
Rising Edge/High-Level Interrupt Selection
16
1
write-only
P17
Rising Edge/High-Level Interrupt Selection
17
1
write-only
P18
Rising Edge/High-Level Interrupt Selection
18
1
write-only
P19
Rising Edge/High-Level Interrupt Selection
19
1
write-only
P2
Rising Edge/High-Level Interrupt Selection
2
1
write-only
P20
Rising Edge/High-Level Interrupt Selection
20
1
write-only
P21
Rising Edge/High-Level Interrupt Selection
21
1
write-only
P22
Rising Edge/High-Level Interrupt Selection
22
1
write-only
P23
Rising Edge/High-Level Interrupt Selection
23
1
write-only
P24
Rising Edge/High-Level Interrupt Selection
24
1
write-only
P25
Rising Edge/High-Level Interrupt Selection
25
1
write-only
P26
Rising Edge/High-Level Interrupt Selection
26
1
write-only
P27
Rising Edge/High-Level Interrupt Selection
27
1
write-only
P28
Rising Edge/High-Level Interrupt Selection
28
1
write-only
P29
Rising Edge/High-Level Interrupt Selection
29
1
write-only
P3
Rising Edge/High-Level Interrupt Selection
3
1
write-only
P30
Rising Edge/High-Level Interrupt Selection
30
1
write-only
P31
Rising Edge/High-Level Interrupt Selection
31
1
write-only
P4
Rising Edge/High-Level Interrupt Selection
4
1
write-only
P5
Rising Edge/High-Level Interrupt Selection
5
1
write-only
P6
Rising Edge/High-Level Interrupt Selection
6
1
write-only
P7
Rising Edge/High-Level Interrupt Selection
7
1
write-only
P8
Rising Edge/High-Level Interrupt Selection
8
1
write-only
P9
Rising Edge/High-Level Interrupt Selection
9
1
write-only
SCDR
Slow Clock Divider Debouncing Register
0x8C
32
read-write
n
0x0
0x0
DIV
Slow Clock Divider Selection for Debouncing
0
14
read-write
SCHMITT
Schmitt Trigger Register
0x100
32
read-write
n
0x0
0x0
SCHMITT0
Schmitt Trigger Control
0
1
read-write
SCHMITT1
Schmitt Trigger Control
1
1
read-write
SCHMITT10
Schmitt Trigger Control
10
1
read-write
SCHMITT11
Schmitt Trigger Control
11
1
read-write
SCHMITT12
Schmitt Trigger Control
12
1
read-write
SCHMITT13
Schmitt Trigger Control
13
1
read-write
SCHMITT14
Schmitt Trigger Control
14
1
read-write
SCHMITT15
Schmitt Trigger Control
15
1
read-write
SCHMITT16
Schmitt Trigger Control
16
1
read-write
SCHMITT17
Schmitt Trigger Control
17
1
read-write
SCHMITT18
Schmitt Trigger Control
18
1
read-write
SCHMITT19
Schmitt Trigger Control
19
1
read-write
SCHMITT2
Schmitt Trigger Control
2
1
read-write
SCHMITT20
Schmitt Trigger Control
20
1
read-write
SCHMITT21
Schmitt Trigger Control
21
1
read-write
SCHMITT22
Schmitt Trigger Control
22
1
read-write
SCHMITT23
Schmitt Trigger Control
23
1
read-write
SCHMITT24
Schmitt Trigger Control
24
1
read-write
SCHMITT25
Schmitt Trigger Control
25
1
read-write
SCHMITT26
Schmitt Trigger Control
26
1
read-write
SCHMITT27
Schmitt Trigger Control
27
1
read-write
SCHMITT28
Schmitt Trigger Control
28
1
read-write
SCHMITT29
Schmitt Trigger Control
29
1
read-write
SCHMITT3
Schmitt Trigger Control
3
1
read-write
SCHMITT30
Schmitt Trigger Control
30
1
read-write
SCHMITT31
Schmitt Trigger Control
31
1
read-write
SCHMITT4
Schmitt Trigger Control
4
1
read-write
SCHMITT5
Schmitt Trigger Control
5
1
read-write
SCHMITT6
Schmitt Trigger Control
6
1
read-write
SCHMITT7
Schmitt Trigger Control
7
1
read-write
SCHMITT8
Schmitt Trigger Control
8
1
read-write
SCHMITT9
Schmitt Trigger Control
9
1
read-write
SODR
Set Output Data Register
0x30
32
write-only
n
0x0
0x0
P0
Set Output Data
0
1
write-only
P1
Set Output Data
1
1
write-only
P10
Set Output Data
10
1
write-only
P11
Set Output Data
11
1
write-only
P12
Set Output Data
12
1
write-only
P13
Set Output Data
13
1
write-only
P14
Set Output Data
14
1
write-only
P15
Set Output Data
15
1
write-only
P16
Set Output Data
16
1
write-only
P17
Set Output Data
17
1
write-only
P18
Set Output Data
18
1
write-only
P19
Set Output Data
19
1
write-only
P2
Set Output Data
2
1
write-only
P20
Set Output Data
20
1
write-only
P21
Set Output Data
21
1
write-only
P22
Set Output Data
22
1
write-only
P23
Set Output Data
23
1
write-only
P24
Set Output Data
24
1
write-only
P25
Set Output Data
25
1
write-only
P26
Set Output Data
26
1
write-only
P27
Set Output Data
27
1
write-only
P28
Set Output Data
28
1
write-only
P29
Set Output Data
29
1
write-only
P3
Set Output Data
3
1
write-only
P30
Set Output Data
30
1
write-only
P31
Set Output Data
31
1
write-only
P4
Set Output Data
4
1
write-only
P5
Set Output Data
5
1
write-only
P6
Set Output Data
6
1
write-only
P7
Set Output Data
7
1
write-only
P8
Set Output Data
8
1
write-only
P9
Set Output Data
9
1
write-only
WPMR
Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protection Enable
0
1
read-write
WPKEY
Write Protection Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
0x50494F
WPSR
Write Protection Status Register
0xE8
32
read-only
n
0x0
0x0
WPVS
Write Protection Violation Status
0
1
read-only
WPVSRC
Write Protection Violation Source
8
16
read-only
PMC
Power Management Controller
PMC
0x0
0x0
0x200
registers
n
PMC
5
CKGR_MCFR
Main Clock Frequency Register
0x24
32
read-write
n
0x0
0x0
MAINF
Main Clock Frequency
0
16
read-write
MAINFRDY
Main Clock Frequency Measure Ready
16
1
read-write
RCMEAS
RC Oscillator Frequency Measure (write-only)
20
1
read-write
CKGR_MOR
Main Oscillator Register
0x20
32
read-write
n
0x0
0x0
CFDEN
Clock Failure Detector Enable
25
1
read-write
KEY
Write Access Password
16
8
read-write
PASSWD
Writing any other value in this field aborts the write operation.Always reads as 0.
0x37
MOSCRCEN
Main On-Chip RC Oscillator Enable
3
1
read-write
MOSCRCF
Main On-Chip RC Oscillator Frequency Selection
4
3
read-write
4_MHz
The Fast RC Oscillator Frequency is at 4 MHz (default)
0x0
8_MHz
The Fast RC Oscillator Frequency is at 8 MHz
0x1
12_MHz
The Fast RC Oscillator Frequency is at 12 MHz
0x2
MOSCSEL
Main Oscillator Selection
24
1
read-write
MOSCXTBY
Main Crystal Oscillator Bypass
1
1
read-write
MOSCXTEN
Main Crystal Oscillator Enable
0
1
read-write
MOSCXTST
Main Crystal Oscillator Start-up Time
8
8
read-write
WAITMODE
Wait Mode Command (Write-only)
2
1
read-write
XT32KFME
Slow Crystal Oscillator Frequency Monitoring Enable
26
1
read-write
CKGR_PLLAR
PLLA Register
0x28
32
read-write
n
0x0
0x0
MULA
PLLA Multiplier
16
11
read-write
PLLACOUNT
PLLA Counter
8
6
read-write
PLLAEN
PLLA Control
0
8
read-write
CKGR_PLLBR
PLLB Register
0x2C
32
read-write
n
0x0
0x0
DIVB
PLLB Front-End Divider
0
8
read-write
MULB
PLLB Multiplier
16
11
read-write
PLLBCOUNT
PLLB Counter
8
6
read-write
SRCB
Source for PLLB
29
1
read-write
MAINCK_IN_PLLB
The PLLB input clock is Main Clock
0
PLLA_IN_PLLB
The PLLB input clock is PLLA output
1
CPFSMR
Coprocessor Fast Startup Mode Register
0x7C
32
read-write
n
0x0
0x0
FSTT0
Fast Startup Input Enable 0
0
1
read-write
FSTT1
Fast Startup Input Enable 1
1
1
read-write
FSTT10
Fast Startup Input Enable 10
10
1
read-write
FSTT11
Fast Startup Input Enable 11
11
1
read-write
FSTT12
Fast Startup Input Enable 12
12
1
read-write
FSTT13
Fast Startup Input Enable 13
13
1
read-write
FSTT14
Fast Startup Input Enable 14
14
1
read-write
FSTT15
Fast Startup Input Enable 15
15
1
read-write
FSTT2
Fast Startup Input Enable 2
2
1
read-write
FSTT3
Fast Startup Input Enable 3
3
1
read-write
FSTT4
Fast Startup Input Enable 4
4
1
read-write
FSTT5
Fast Startup Input Enable 5
5
1
read-write
FSTT6
Fast Startup Input Enable 6
6
1
read-write
FSTT7
Fast Startup Input Enable 7
7
1
read-write
FSTT8
Fast Startup Input Enable 8
8
1
read-write
FSTT9
Fast Startup Input Enable 9
9
1
read-write
RTCAL
RTC Alarm Enable
17
1
read-write
RTTAL
RTT Alarm Enable
16
1
read-write
FOCR
Fault Output Clear Register
0x78
32
write-only
n
0x0
0x0
FOCLR
Fault Output Clear
0
1
write-only
FSMR
Fast Startup Mode Register
0x70
32
read-write
n
0x0
0x0
FLPM
Flash Low-power Mode
21
2
read-write
FLASH_STANDBY
Flash is in Standby Mode when system enters Wait Mode
0x0
FLASH_DEEP_POWERDOWN
Flash is in Deep-power-down mode when system enters Wait Mode
0x1
FLASH_IDLE
Idle mode
0x2
FSTT0
Fast Startup Input Enable 0
0
1
read-write
FSTT1
Fast Startup Input Enable 1
1
1
read-write
FSTT10
Fast Startup Input Enable 10
10
1
read-write
FSTT11
Fast Startup Input Enable 11
11
1
read-write
FSTT12
Fast Startup Input Enable 12
12
1
read-write
FSTT13
Fast Startup Input Enable 13
13
1
read-write
FSTT14
Fast Startup Input Enable 14
14
1
read-write
FSTT15
Fast Startup Input Enable 15
15
1
read-write
FSTT2
Fast Startup Input Enable 2
2
1
read-write
FSTT3
Fast Startup Input Enable 3
3
1
read-write
FSTT4
Fast Startup Input Enable 4
4
1
read-write
FSTT5
Fast Startup Input Enable 5
5
1
read-write
FSTT6
Fast Startup Input Enable 6
6
1
read-write
FSTT7
Fast Startup Input Enable 7
7
1
read-write
FSTT8
Fast Startup Input Enable 8
8
1
read-write
FSTT9
Fast Startup Input Enable 9
9
1
read-write
LPM
Low-power Mode
20
1
read-write
RTCAL
RTC Alarm Enable
17
1
read-write
RTTAL
RTT Alarm Enable
16
1
read-write
FSPR
Fast Startup Polarity Register
0x74
32
read-write
n
0x0
0x0
FSTP0
Fast Startup Input Polarityx
0
1
read-write
FSTP1
Fast Startup Input Polarityx
1
1
read-write
FSTP10
Fast Startup Input Polarityx
10
1
read-write
FSTP11
Fast Startup Input Polarityx
11
1
read-write
FSTP12
Fast Startup Input Polarityx
12
1
read-write
FSTP13
Fast Startup Input Polarityx
13
1
read-write
FSTP14
Fast Startup Input Polarityx
14
1
read-write
FSTP15
Fast Startup Input Polarityx
15
1
read-write
FSTP2
Fast Startup Input Polarityx
2
1
read-write
FSTP3
Fast Startup Input Polarityx
3
1
read-write
FSTP4
Fast Startup Input Polarityx
4
1
read-write
FSTP5
Fast Startup Input Polarityx
5
1
read-write
FSTP6
Fast Startup Input Polarityx
6
1
read-write
FSTP7
Fast Startup Input Polarityx
7
1
read-write
FSTP8
Fast Startup Input Polarityx
8
1
read-write
FSTP9
Fast Startup Input Polarityx
9
1
read-write
IDR
Interrupt Disable Register
0x64
32
write-only
n
0x0
0x0
CFDEV
Clock Failure Detector Event Interrupt Disable
18
1
write-only
LOCKA
PLLA Lock Interrupt Disable
1
1
write-only
LOCKB
PLLB Lock Interrupt Disable
2
1
write-only
MCKRDY
Master Clock Ready Interrupt Disable
3
1
write-only
MOSCRCS
Main On-Chip RC Status Interrupt Disable
17
1
write-only
MOSCSELS
Main Oscillator Selection Status Interrupt Disable
16
1
write-only
MOSCXTS
Main Crystal Oscillator Status Interrupt Disable
0
1
write-only
PCKRDY0
Programmable Clock Ready 0 Interrupt Disable
8
1
write-only
PCKRDY1
Programmable Clock Ready 1 Interrupt Disable
9
1
write-only
PCKRDY2
Programmable Clock Ready 2 Interrupt Disable
10
1
write-only
XT32KERR
Slow Crystal Oscillator Error Interrupt Disable
21
1
write-only
IER
Interrupt Enable Register
0x60
32
write-only
n
0x0
0x0
CFDEV
Clock Failure Detector Event Interrupt Enable
18
1
write-only
LOCKA
PLLA Lock Interrupt Enable
1
1
write-only
LOCKB
PLLB Lock Interrupt Enable
2
1
write-only
MCKRDY
Master Clock Ready Interrupt Enable
3
1
write-only
MOSCRCS
Main On-Chip RC Status Interrupt Enable
17
1
write-only
MOSCSELS
Main Oscillator Selection Status Interrupt Enable
16
1
write-only
MOSCXTS
Main Crystal Oscillator Status Interrupt Enable
0
1
write-only
PCKRDY0
Programmable Clock Ready 0 Interrupt Enable
8
1
write-only
PCKRDY1
Programmable Clock Ready 1 Interrupt Enable
9
1
write-only
PCKRDY2
Programmable Clock Ready 2 Interrupt Enable
10
1
write-only
XT32KERR
Slow Crystal Oscillator Error Interrupt Enable
21
1
write-only
IMR
Interrupt Mask Register
0x6C
32
read-only
n
0x0
0x0
CFDEV
Clock Failure Detector Event Interrupt Mask
18
1
read-only
LOCKA
PLLA Lock Interrupt Mask
1
1
read-only
LOCKB
PLLB Lock Interrupt Mask
2
1
read-only
MCKRDY
Master Clock Ready Interrupt Mask
3
1
read-only
MOSCRCS
Main On-Chip RC Status Interrupt Mask
17
1
read-only
MOSCSELS
Main Oscillator Selection Status Interrupt Mask
16
1
read-only
MOSCXTS
Main Crystal Oscillator Status Interrupt Mask
0
1
read-only
PCKRDY0
Programmable Clock Ready 0 Interrupt Mask
8
1
read-only
PCKRDY1
Programmable Clock Ready 1 Interrupt Mask
9
1
read-only
PCKRDY2
Programmable Clock Ready 2 Interrupt Mask
10
1
read-only
XT32KERR
Slow Crystal Oscillator Error Interrupt Mask
21
1
read-only
MCKR
Master Clock Register
0x30
32
read-write
n
0x0
0x0
CPCSS
Coprocessor Master Clock Source Selection
16
3
read-write
SLOW_CLK
Slow Clock is selected
0x0
MAIN_CLK
Main Clock is selected
0x1
PLLA_CLK
PLLA Clock is selected
0x2
PLLB_CLK
PLLB Clock is selected
0x3
MCK
Master Clock is selected
0x4
CPPRES
Coprocessor Programmable Clock Prescaler
20
4
read-write
CSS
Master Clock Source Selection
0
2
read-write
SLOW_CLK
Slow Clock is selected
0x0
MAIN_CLK
Main Clock is selected
0x1
PLLA_CLK
PLLA Clock is selected
0x2
PLLB_CLK
PLLBClock is selected
0x3
PLLADIV2
PLLA Divisor by 2
12
1
read-write
PLLBDIV2
13
1
read-write
PRES
Processor Clock Prescaler
4
3
read-write
CLK_1
Selected clock
0x0
CLK_2
Selected clock divided by 2
0x1
CLK_4
Selected clock divided by 4
0x2
CLK_8
Selected clock divided by 8
0x3
CLK_16
Selected clock divided by 16
0x4
CLK_32
Selected clock divided by 32
0x5
CLK_64
Selected clock divided by 64
0x6
CLK_3
Selected clock divided by 3
0x7
OCR
Oscillator Calibration Register
0x110
32
read-write
n
0x0
0x0
CAL12
RC Oscillator Calibration bits for 12 MHz
16
7
read-write
CAL4
RC Oscillator Calibration bits for 4 MHz
0
7
read-write
CAL8
RC Oscillator Calibration bits for 8 MHz
8
7
read-write
SEL12
Selection of RC Oscillator Calibration bits for 12 MHz
23
1
read-write
SEL4
Selection of RC Oscillator Calibration bits for 4 MHz
7
1
read-write
SEL8
Selection of RC Oscillator Calibration bits for 8 MHz
15
1
read-write
PCDR0
Peripheral Clock Disable Register 0
0x14
32
write-only
n
0x0
0x0
PID10
Peripheral Clock 10 Disable
10
1
write-only
PID11
Peripheral Clock 11 Disable
11
1
write-only
PID12
Peripheral Clock 12 Disable
12
1
write-only
PID13
Peripheral Clock 13 Disable
13
1
write-only
PID14
Peripheral Clock 14 Disable
14
1
write-only
PID15
Peripheral Clock 15 Disable
15
1
write-only
PID16
Peripheral Clock 16 Disable
16
1
write-only
PID17
Peripheral Clock 17 Disable
17
1
write-only
PID18
Peripheral Clock 18 Disable
18
1
write-only
PID19
Peripheral Clock 19 Disable
19
1
write-only
PID20
Peripheral Clock 20 Disable
20
1
write-only
PID21
Peripheral Clock 21 Disable
21
1
write-only
PID22
Peripheral Clock 22 Disable
22
1
write-only
PID23
Peripheral Clock 23 Disable
23
1
write-only
PID24
Peripheral Clock 24 Disable
24
1
write-only
PID25
Peripheral Clock 25 Disable
25
1
write-only
PID26
Peripheral Clock 26 Disable
26
1
write-only
PID27
Peripheral Clock 27 Disable
27
1
write-only
PID28
Peripheral Clock 28 Disable
28
1
write-only
PID29
Peripheral Clock 29 Disable
29
1
write-only
PID31
Peripheral Clock 31 Disable
31
1
write-only
PID8
Peripheral Clock 8 Disable
8
1
write-only
PID9
Peripheral Clock 9 Disable
9
1
write-only
PCDR1
Peripheral Clock Disable Register 1
0x104
32
write-only
n
0x0
0x0
PID32
Peripheral Clock 32 Disable
0
1
write-only
PID33
Peripheral Clock 33 Disable
1
1
write-only
PID34
Peripheral Clock 34 Disable
2
1
write-only
PID35
Peripheral Clock 35 Disable
3
1
write-only
PID36
Peripheral Clock 36 Disable
4
1
write-only
PID37
Peripheral Clock 37 Disable
5
1
write-only
PID38
Peripheral Clock 38 Disable
6
1
write-only
PID39
Peripheral Clock 39 Disable
7
1
write-only
PID40
Peripheral Clock 40 Disable
8
1
write-only
PID41
Peripheral Clock 41 Disable
9
1
write-only
PID42
Peripheral Clock 42 Disable
10
1
write-only
PID43
Peripheral Clock 43 Disable
11
1
write-only
PCER0
Peripheral Clock Enable Register 0
0x10
32
write-only
n
0x0
0x0
PID10
Peripheral Clock 10 Enable
10
1
write-only
PID11
Peripheral Clock 11 Enable
11
1
write-only
PID12
Peripheral Clock 12 Enable
12
1
write-only
PID13
Peripheral Clock 13 Enable
13
1
write-only
PID14
Peripheral Clock 14 Enable
14
1
write-only
PID15
Peripheral Clock 15 Enable
15
1
write-only
PID16
Peripheral Clock 16 Enable
16
1
write-only
PID17
Peripheral Clock 17 Enable
17
1
write-only
PID18
Peripheral Clock 18 Enable
18
1
write-only
PID19
Peripheral Clock 19 Enable
19
1
write-only
PID20
Peripheral Clock 20 Enable
20
1
write-only
PID21
Peripheral Clock 21 Enable
21
1
write-only
PID22
Peripheral Clock 22 Enable
22
1
write-only
PID23
Peripheral Clock 23 Enable
23
1
write-only
PID24
Peripheral Clock 24 Enable
24
1
write-only
PID25
Peripheral Clock 25 Enable
25
1
write-only
PID26
Peripheral Clock 26 Enable
26
1
write-only
PID27
Peripheral Clock 27 Enable
27
1
write-only
PID28
Peripheral Clock 28 Enable
28
1
write-only
PID29
Peripheral Clock 29 Enable
29
1
write-only
PID31
Peripheral Clock 31 Enable
31
1
write-only
PID8
Peripheral Clock 8 Enable
8
1
write-only
PID9
Peripheral Clock 9 Enable
9
1
write-only
PCER1
Peripheral Clock Enable Register 1
0x100
32
write-only
n
0x0
0x0
PID32
Peripheral Clock 32 Enable
0
1
write-only
PID33
Peripheral Clock 33 Enable
1
1
write-only
PID34
Peripheral Clock 34 Enable
2
1
write-only
PID35
Peripheral Clock 35 Enable
3
1
write-only
PID36
Peripheral Clock 36 Enable
4
1
write-only
PID37
Peripheral Clock 37 Enable
5
1
write-only
PID38
Peripheral Clock 38 Enable
6
1
write-only
PID39
Peripheral Clock 39 Enable
7
1
write-only
PID40
Peripheral Clock 40 Enable
8
1
write-only
PID41
Peripheral Clock 41 Enable
9
1
write-only
PID42
Peripheral Clock 42 Enable
10
1
write-only
PID43
Peripheral Clock 43 Enable
11
1
write-only
PCK0
Programmable Clock 0 Register
0x40
32
read-write
n
CSS
Master Clock Source Selection
0
3
read-write
SLOW_CLK
Slow Clock is selected
0x0
MAIN_CLK
Main Clock is selected
0x1
PLLA_CLK
PLLA Clock is selected
0x2
PLLB_CLK
PLLB Clock is selected
0x3
MCK
Master Clock is selected
0x4
PRES
Programmable Clock Prescaler
4
3
read-write
CLK_1
Selected clock
0x0
CLK_2
Selected clock divided by 2
0x1
CLK_4
Selected clock divided by 4
0x2
CLK_8
Selected clock divided by 8
0x3
CLK_16
Selected clock divided by 16
0x4
CLK_32
Selected clock divided by 32
0x5
CLK_64
Selected clock divided by 64
0x6
PCK1
Programmable Clock 0 Register
0x44
32
read-write
n
CSS
Master Clock Source Selection
0
3
read-write
SLOW_CLK
Slow Clock is selected
0x0
MAIN_CLK
Main Clock is selected
0x1
PLLA_CLK
PLLA Clock is selected
0x2
PLLB_CLK
PLLB Clock is selected
0x3
MCK
Master Clock is selected
0x4
PRES
Programmable Clock Prescaler
4
3
read-write
CLK_1
Selected clock
0x0
CLK_2
Selected clock divided by 2
0x1
CLK_4
Selected clock divided by 4
0x2
CLK_8
Selected clock divided by 8
0x3
CLK_16
Selected clock divided by 16
0x4
CLK_32
Selected clock divided by 32
0x5
CLK_64
Selected clock divided by 64
0x6
PCK2
Programmable Clock 0 Register
0x48
32
read-write
n
CSS
Master Clock Source Selection
0
3
read-write
SLOW_CLK
Slow Clock is selected
0x0
MAIN_CLK
Main Clock is selected
0x1
PLLA_CLK
PLLA Clock is selected
0x2
PLLB_CLK
PLLB Clock is selected
0x3
MCK
Master Clock is selected
0x4
PRES
Programmable Clock Prescaler
4
3
read-write
CLK_1
Selected clock
0x0
CLK_2
Selected clock divided by 2
0x1
CLK_4
Selected clock divided by 4
0x2
CLK_8
Selected clock divided by 8
0x3
CLK_16
Selected clock divided by 16
0x4
CLK_32
Selected clock divided by 32
0x5
CLK_64
Selected clock divided by 64
0x6
PCK[0]
Programmable Clock 0 Register
0x80
32
read-write
n
0x0
0x0
CSS
Master Clock Source Selection
0
3
read-write
SLOW_CLK
Slow Clock is selected
0x0
MAIN_CLK
Main Clock is selected
0x1
PLLA_CLK
PLLA Clock is selected
0x2
PLLB_CLK
PLLB Clock is selected
0x3
MCK
Master Clock is selected
0x4
PRES
Programmable Clock Prescaler
4
3
read-write
CLK_1
Selected clock
0x0
CLK_2
Selected clock divided by 2
0x1
CLK_4
Selected clock divided by 4
0x2
CLK_8
Selected clock divided by 8
0x3
CLK_16
Selected clock divided by 16
0x4
CLK_32
Selected clock divided by 32
0x5
CLK_64
Selected clock divided by 64
0x6
PCK[1]
Programmable Clock 0 Register
0xC4
32
read-write
n
0x0
0x0
CSS
Master Clock Source Selection
0
3
read-write
SLOW_CLK
Slow Clock is selected
0x0
MAIN_CLK
Main Clock is selected
0x1
PLLA_CLK
PLLA Clock is selected
0x2
PLLB_CLK
PLLB Clock is selected
0x3
MCK
Master Clock is selected
0x4
PRES
Programmable Clock Prescaler
4
3
read-write
CLK_1
Selected clock
0x0
CLK_2
Selected clock divided by 2
0x1
CLK_4
Selected clock divided by 4
0x2
CLK_8
Selected clock divided by 8
0x3
CLK_16
Selected clock divided by 16
0x4
CLK_32
Selected clock divided by 32
0x5
CLK_64
Selected clock divided by 64
0x6
PCK[2]
Programmable Clock 0 Register
0x10C
32
read-write
n
0x0
0x0
CSS
Master Clock Source Selection
0
3
read-write
SLOW_CLK
Slow Clock is selected
0x0
MAIN_CLK
Main Clock is selected
0x1
PLLA_CLK
PLLA Clock is selected
0x2
PLLB_CLK
PLLB Clock is selected
0x3
MCK
Master Clock is selected
0x4
PRES
Programmable Clock Prescaler
4
3
read-write
CLK_1
Selected clock
0x0
CLK_2
Selected clock divided by 2
0x1
CLK_4
Selected clock divided by 4
0x2
CLK_8
Selected clock divided by 8
0x3
CLK_16
Selected clock divided by 16
0x4
CLK_32
Selected clock divided by 32
0x5
CLK_64
Selected clock divided by 64
0x6
PCSR0
Peripheral Clock Status Register 0
0x18
32
read-only
n
0x0
0x0
PID10
Peripheral Clock 10 Status
10
1
read-only
PID11
Peripheral Clock 11 Status
11
1
read-only
PID12
Peripheral Clock 12 Status
12
1
read-only
PID13
Peripheral Clock 13 Status
13
1
read-only
PID14
Peripheral Clock 14 Status
14
1
read-only
PID15
Peripheral Clock 15 Status
15
1
read-only
PID16
Peripheral Clock 16 Status
16
1
read-only
PID17
Peripheral Clock 17 Status
17
1
read-only
PID18
Peripheral Clock 18 Status
18
1
read-only
PID19
Peripheral Clock 19 Status
19
1
read-only
PID20
Peripheral Clock 20 Status
20
1
read-only
PID21
Peripheral Clock 21 Status
21
1
read-only
PID22
Peripheral Clock 22 Status
22
1
read-only
PID23
Peripheral Clock 23 Status
23
1
read-only
PID24
Peripheral Clock 24 Status
24
1
read-only
PID25
Peripheral Clock 25 Status
25
1
read-only
PID26
Peripheral Clock 26 Status
26
1
read-only
PID27
Peripheral Clock 27 Status
27
1
read-only
PID28
Peripheral Clock 28 Status
28
1
read-only
PID29
Peripheral Clock 29 Status
29
1
read-only
PID31
Peripheral Clock 31 Status
31
1
read-only
PID8
Peripheral Clock 8 Status
8
1
read-only
PID9
Peripheral Clock 9 Status
9
1
read-only
PCSR1
Peripheral Clock Status Register 1
0x108
32
read-only
n
0x0
0x0
PID32
Peripheral Clock 32 Status
0
1
read-only
PID33
Peripheral Clock 33 Status
1
1
read-only
PID34
Peripheral Clock 34 Status
2
1
read-only
PID35
Peripheral Clock 35 Status
3
1
read-only
PID36
Peripheral Clock 36 Status
4
1
read-only
PID37
Peripheral Clock 37 Status
5
1
read-only
PID38
Peripheral Clock 38 Status
6
1
read-only
PID39
Peripheral Clock 39 Status
7
1
read-only
PID40
Peripheral Clock 40 Status
8
1
read-only
PID41
Peripheral Clock 41 Status
9
1
read-only
PID42
Peripheral Clock 42 Status
10
1
read-only
PID43
Peripheral Clock 43 Status
11
1
read-only
SCDR
System Clock Disable Register
0x4
32
write-only
n
0x0
0x0
CPBMCK
Coprocessor Bus Master Clocks Disable
17
1
write-only
CPCK
Coprocessor Clocks Disable
16
1
write-only
CPKEY
Coprocessor Clocks Disable Key
20
4
write-only
PASSWD
This field must be written to 0xA in order to validate CPCK field.
0xA
PCK0
Programmable Clock 0 Output Disable
8
1
write-only
PCK1
Programmable Clock 1 Output Disable
9
1
write-only
PCK2
Programmable Clock 2 Output Disable
10
1
write-only
SCER
System Clock Enable Register
0x0
32
write-only
n
0x0
0x0
CPBMCK
Coprocessor Bus Master Clocks Enable
17
1
write-only
CPCK
Coprocessor (Second Processor) Clocks Enable
16
1
write-only
CPKEY
Coprocessor Clocks Enable Key
20
4
write-only
PASSWD
This field must be written to 0xA in order to validate CPCK field.
0xA
PCK0
Programmable Clock 0 Output Enable
8
1
write-only
PCK1
Programmable Clock 1 Output Enable
9
1
write-only
PCK2
Programmable Clock 2 Output Enable
10
1
write-only
SCSR
System Clock Status Register
0x8
32
read-only
n
0x0
0x0
CPBMCK
Coprocessor Bus Master Clock Status
17
1
read-only
CPCK
Coprocessor (Second Processor) Clocks Status
16
1
read-only
PCK0
Programmable Clock 0 Output Status
8
1
read-only
PCK1
Programmable Clock 1 Output Status
9
1
read-only
PCK2
Programmable Clock 2 Output Status
10
1
read-only
SR
Status Register
0x68
32
read-only
n
0x0
0x0
CFDEV
Clock Failure Detector Event
18
1
read-only
CFDS
Clock Failure Detector Status
19
1
read-only
FOS
Clock Failure Detector Fault Output Status
20
1
read-only
LOCKA
PLLA Lock Status
1
1
read-only
LOCKB
PLLB Lock Status
2
1
read-only
MCKRDY
Master Clock Status
3
1
read-only
MOSCRCS
Main On-Chip RC Oscillator Status
17
1
read-only
MOSCSELS
Main Oscillator Selection Status
16
1
read-only
MOSCXTS
Main Crystal Oscillator Status
0
1
read-only
OSCSELS
Slow Clock Oscillator Selection
7
1
read-only
PCKRDY0
Programmable Clock Ready Status
8
1
read-only
PCKRDY1
Programmable Clock Ready Status
9
1
read-only
PCKRDY2
Programmable Clock Ready Status
10
1
read-only
XT32KERR
Slow Crystal Oscillator Error
21
1
read-only
WPMR
Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protection Enable
0
1
read-write
WPKEY
Write Protection Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
0x504D43
WPSR
Write Protection Status Register
0xE8
32
read-only
n
0x0
0x0
WPVS
Write Protection Violation Status
0
1
read-only
WPVSRC
Write Protection Violation Source
8
16
read-only
PWM
Pulse Width Modulation Controller
PWM
0x0
0x0
0x50
registers
n
PWM
41
CCNT0
PWM Channel Counter Register (ch_num = 0)
0x20C
32
read-only
n
0x0
0x0
CNT
Channel Counter Register
0
32
read-only
CCNT1
PWM Channel Counter Register (ch_num = 1)
0x22C
32
read-only
n
0x0
0x0
CNT
Channel Counter Register
0
32
read-only
CCNT2
PWM Channel Counter Register (ch_num = 2)
0x24C
32
read-only
n
0x0
0x0
CNT
Channel Counter Register
0
32
read-only
CCNT3
PWM Channel Counter Register (ch_num = 3)
0x26C
32
read-only
n
0x0
0x0
CNT
Channel Counter Register
0
32
read-only
CDTY0
PWM Channel Duty Cycle Register (ch_num = 0)
0x204
32
read-write
n
0x0
0x0
CDTY
Channel Duty Cycle
0
32
read-write
CDTY1
PWM Channel Duty Cycle Register (ch_num = 1)
0x224
32
read-write
n
0x0
0x0
CDTY
Channel Duty Cycle
0
32
read-write
CDTY2
PWM Channel Duty Cycle Register (ch_num = 2)
0x244
32
read-write
n
0x0
0x0
CDTY
Channel Duty Cycle
0
32
read-write
CDTY3
PWM Channel Duty Cycle Register (ch_num = 3)
0x264
32
read-write
n
0x0
0x0
CDTY
Channel Duty Cycle
0
32
read-write
CMR0
PWM Channel Mode Register (ch_num = 0)
0x200
32
read-write
n
0x0
0x0
CALG
Channel Alignment
8
1
read-write
CPD
Channel Update Period
10
1
read-write
CPOL
Channel Polarity
9
1
read-write
CPRE
Channel Pre-scaler
0
4
read-write
MCK
Master Clock
0x0
MCKDIV2
Master Clock divided by 2
0x1
MCKDIV4
Master Clock divided by 4
0x2
MCKDIV8
Master Clock divided by 8
0x3
MCKDIV16
Master Clock divided by 16
0x4
MCKDIV32
Master Clock divided by 32
0x5
MCKDIV64
Master Clock divided by 64
0x6
MCKDIV128
Master Clock divided by 128
0x7
MCKDIV256
Master Clock divided by 256
0x8
MCKDIV512
Master Clock divided by 512
0x9
MCKDIV1024
Master Clock divided by 1024
0xA
CLKA
Clock A
0xB
CLKB
Clock B
0xC
CMR1
PWM Channel Mode Register (ch_num = 1)
0x220
32
read-write
n
0x0
0x0
CALG
Channel Alignment
8
1
read-write
CPD
Channel Update Period
10
1
read-write
CPOL
Channel Polarity
9
1
read-write
CPRE
Channel Pre-scaler
0
4
read-write
MCK
Master Clock
0x0
MCKDIV2
Master Clock divided by 2
0x1
MCKDIV4
Master Clock divided by 4
0x2
MCKDIV8
Master Clock divided by 8
0x3
MCKDIV16
Master Clock divided by 16
0x4
MCKDIV32
Master Clock divided by 32
0x5
MCKDIV64
Master Clock divided by 64
0x6
MCKDIV128
Master Clock divided by 128
0x7
MCKDIV256
Master Clock divided by 256
0x8
MCKDIV512
Master Clock divided by 512
0x9
MCKDIV1024
Master Clock divided by 1024
0xA
CLKA
Clock A
0xB
CLKB
Clock B
0xC
CMR2
PWM Channel Mode Register (ch_num = 2)
0x240
32
read-write
n
0x0
0x0
CALG
Channel Alignment
8
1
read-write
CPD
Channel Update Period
10
1
read-write
CPOL
Channel Polarity
9
1
read-write
CPRE
Channel Pre-scaler
0
4
read-write
MCK
Master Clock
0x0
MCKDIV2
Master Clock divided by 2
0x1
MCKDIV4
Master Clock divided by 4
0x2
MCKDIV8
Master Clock divided by 8
0x3
MCKDIV16
Master Clock divided by 16
0x4
MCKDIV32
Master Clock divided by 32
0x5
MCKDIV64
Master Clock divided by 64
0x6
MCKDIV128
Master Clock divided by 128
0x7
MCKDIV256
Master Clock divided by 256
0x8
MCKDIV512
Master Clock divided by 512
0x9
MCKDIV1024
Master Clock divided by 1024
0xA
CLKA
Clock A
0xB
CLKB
Clock B
0xC
CMR3
PWM Channel Mode Register (ch_num = 3)
0x260
32
read-write
n
0x0
0x0
CALG
Channel Alignment
8
1
read-write
CPD
Channel Update Period
10
1
read-write
CPOL
Channel Polarity
9
1
read-write
CPRE
Channel Pre-scaler
0
4
read-write
MCK
Master Clock
0x0
MCKDIV2
Master Clock divided by 2
0x1
MCKDIV4
Master Clock divided by 4
0x2
MCKDIV8
Master Clock divided by 8
0x3
MCKDIV16
Master Clock divided by 16
0x4
MCKDIV32
Master Clock divided by 32
0x5
MCKDIV64
Master Clock divided by 64
0x6
MCKDIV128
Master Clock divided by 128
0x7
MCKDIV256
Master Clock divided by 256
0x8
MCKDIV512
Master Clock divided by 512
0x9
MCKDIV1024
Master Clock divided by 1024
0xA
CLKA
Clock A
0xB
CLKB
Clock B
0xC
CPRD0
PWM Channel Period Register (ch_num = 0)
0x208
32
read-write
n
0x0
0x0
CPRD
Channel Period
0
32
read-write
CPRD1
PWM Channel Period Register (ch_num = 1)
0x228
32
read-write
n
0x0
0x0
CPRD
Channel Period
0
32
read-write
CPRD2
PWM Channel Period Register (ch_num = 2)
0x248
32
read-write
n
0x0
0x0
CPRD
Channel Period
0
32
read-write
CPRD3
PWM Channel Period Register (ch_num = 3)
0x268
32
read-write
n
0x0
0x0
CPRD
Channel Period
0
32
read-write
CUPD0
PWM Channel Update Register (ch_num = 0)
0x210
32
write-only
n
0x0
0x0
CUPD
0
32
write-only
CUPD1
PWM Channel Update Register (ch_num = 1)
0x230
32
write-only
n
0x0
0x0
CUPD
0
32
write-only
CUPD2
PWM Channel Update Register (ch_num = 2)
0x250
32
write-only
n
0x0
0x0
CUPD
0
32
write-only
CUPD3
PWM Channel Update Register (ch_num = 3)
0x270
32
write-only
n
0x0
0x0
CUPD
0
32
write-only
DIS
PWM Disable Register
0x8
32
write-only
n
0x0
0x0
CHID0
Channel ID
0
1
write-only
CHID1
Channel ID
1
1
write-only
CHID2
Channel ID
2
1
write-only
CHID3
Channel ID
3
1
write-only
ENA
PWM Enable Register
0x4
32
write-only
n
0x0
0x0
CHID0
Channel ID
0
1
write-only
CHID1
Channel ID
1
1
write-only
CHID2
Channel ID
2
1
write-only
CHID3
Channel ID
3
1
write-only
IDR
PWM Interrupt Disable Register
0x14
32
write-only
n
0x0
0x0
CHID0
Channel ID.
0
1
write-only
CHID1
Channel ID.
1
1
write-only
CHID2
Channel ID.
2
1
write-only
CHID3
Channel ID.
3
1
write-only
IER
PWM Interrupt Enable Register
0x10
32
write-only
n
0x0
0x0
CHID0
Channel ID.
0
1
write-only
CHID1
Channel ID.
1
1
write-only
CHID2
Channel ID.
2
1
write-only
CHID3
Channel ID.
3
1
write-only
IMR
PWM Interrupt Mask Register
0x18
32
read-only
n
0x0
0x0
CHID0
Channel ID.
0
1
read-only
CHID1
Channel ID.
1
1
read-only
CHID2
Channel ID.
2
1
read-only
CHID3
Channel ID.
3
1
read-only
ISR
PWM Interrupt Status Register
0x1C
32
read-only
n
0x0
0x0
CHID0
Channel ID
0
1
read-only
CHID1
Channel ID
1
1
read-only
CHID2
Channel ID
2
1
read-only
CHID3
Channel ID
3
1
read-only
MR
PWM Mode Register
0x0
32
read-write
n
0x0
0x0
DIVA
CLKA, CLKB Divide Factor
0
8
read-write
CLK_OFF
CLKA, CLKB clock is turned off
0
CLK_DIV1
CLKA, CLKB clock is clock selected by PREA, PREB
1
DIVB
CLKA, CLKB Divide Factor
16
8
read-write
CLK_OFF
CLKA, CLKB clock is turned off
0
CLK_DIV1
CLKA, CLKB clock is clock selected by PREA, PREB
1
PREA
8
4
read-write
MCK
Master Clock
0x0
MCKDIV2
Master Clock divided by 2
0x1
MCKDIV4
Master Clock divided by 4
0x2
MCKDIV8
Master Clock divided by 8
0x3
MCKDIV16
Master Clock divided by 16
0x4
MCKDIV32
Master Clock divided by 32
0x5
MCKDIV64
Master Clock divided by 64
0x6
MCKDIV128
Master Clock divided by 128
0x7
MCKDIV256
Master Clock divided by 256
0x8
MCKDIV512
Master Clock divided by 512
0x9
MCKDIV1024
Master Clock divided by 1024
0xA
PREB
24
4
read-write
MCK
Master Clock
0x0
MCKDIV2
Master Clock divided by 2
0x1
MCKDIV4
Master Clock divided by 4
0x2
MCKDIV8
Master Clock divided by 8
0x3
MCKDIV16
Master Clock divided by 16
0x4
MCKDIV32
Master Clock divided by 32
0x5
MCKDIV64
Master Clock divided by 64
0x6
MCKDIV128
Master Clock divided by 128
0x7
MCKDIV256
Master Clock divided by 256
0x8
MCKDIV512
Master Clock divided by 512
0x9
MCKDIV1024
Master Clock divided by 1024
0xA
SR
PWM Status Register
0xC
32
read-only
n
0x0
0x0
CHID0
Channel ID
0
1
read-only
CHID1
Channel ID
1
1
read-only
CHID2
Channel ID
2
1
read-only
CHID3
Channel ID
3
1
read-only
RSTC
Reset Controller
SYSC
0x0
0x0
0x200
registers
n
CPMR
Coprocessor Mode Register
0xC
32
read-write
n
0x0
0x0
CPEREN
Coprocessor Peripheral Enable
4
1
read-write
CPKEY
Coprocessor System Enable Key
24
8
read-write
PASSWD
Writing any other value in this field aborts the write operation.
0x5A
CPROCEN
Coprocessor (Second Processor) Enable
0
1
read-write
CR
Control Register
0x0
32
write-only
n
0x0
0x0
EXTRST
External Reset
3
1
write-only
KEY
System Reset Key
24
8
write-only
PASSWD
Writing any other value in this field aborts the write operation.
0xA5
PERRST
Peripheral Reset
2
1
write-only
PROCRST
Processor Reset
0
1
write-only
MR
Mode Register
0x8
32
read-write
n
0x0
0x0
ERSTL
External Reset Length
8
4
read-write
KEY
Write Access Password
24
8
read-write
PASSWD
Writing any other value in this field aborts the write operation.Always reads as 0.
0xA5
URSTEN
User Reset Enable
0
1
read-write
URSTIEN
User Reset Interrupt Enable
4
1
read-write
SR
Status Register
0x4
32
read-only
n
0x0
0x0
NRSTL
NRST Pin Level
16
1
read-only
RSTTYP
Reset Type
8
3
read-only
GENERAL_RST
First power-up reset
0x0
BACKUP_RST
Return from Backup Mode
0x1
WDT_RST
Watchdog fault occurred
0x2
SOFT_RST
Processor reset required by the software
0x3
USER_RST
NRST pin detected low
0x4
SRCMP
Software Reset Command in Progress
17
1
read-only
URSTS
User Reset Status
0
1
read-only
RSWDT
Reinforced Safety Watchdog Timer
SYSC
0x0
0x0
0x200
registers
n
CR
Control Register
0x0
32
write-only
n
0x0
0x0
KEY
Password
24
8
write-only
PASSWD
Writing any other value in this field aborts the write operation.
0xC4
WDRSTT
Watchdog Restart
0
1
write-only
MR
Mode Register
0x4
32
read-write
n
0x0
0x0
WDD
Watchdog Delta Value
16
12
read-write
WDDBGHLT
Watchdog Debug Halt
28
1
read-write
WDDIS
Watchdog Disable
15
1
read-write
WDFIEN
Watchdog Fault Interrupt Enable
12
1
read-write
WDIDLEHLT
Watchdog Idle Halt
29
1
read-write
WDRPROC
Watchdog Reset Processor
14
1
read-write
WDRSTEN
Watchdog Reset Enable
13
1
read-write
WDV
Watchdog Counter Value
0
12
read-write
SR
Status Register
0x8
32
read-only
n
0x0
0x0
WDERR
Watchdog Error
1
1
read-only
WDUNF
Watchdog Underflow
0
1
read-only
RTC
Real-time Clock
SYSC
0x0
0x0
0x200
registers
n
CALALR
Calendar Alarm Register
0x14
32
read-write
n
0x0
0x0
DATE
Date Alarm
24
6
read-write
DATEEN
Date Alarm Enable
31
1
read-write
MONTH
Month Alarm
16
5
read-write
MTHEN
Month Alarm Enable
23
1
read-write
CALR
Calendar Register
0xC
32
read-write
n
0x0
0x0
CENT
Current Century
0
7
read-write
DATE
Current Day in Current Month
24
6
read-write
DAY
Current Day in Current Week
21
3
read-write
MONTH
Current Month
16
5
read-write
YEAR
Current Year
8
8
read-write
CR
Control Register
0x0
32
read-write
n
0x0
0x0
CALEVSEL
Calendar Event Selection
16
2
read-write
WEEK
Week change (every Monday at time 00:00:00)
0x0
MONTH
Month change (every 01 of each month at time 00:00:00)
0x1
YEAR
Year change (every January 1 at time 00:00:00)
0x2
TIMEVSEL
Time Event Selection
8
2
read-write
MINUTE
Minute change
0x0
HOUR
Hour change
0x1
MIDNIGHT
Every day at midnight
0x2
NOON
Every day at noon
0x3
UPDCAL
Update Request Calendar Register
1
1
read-write
UPDTIM
Update Request Time Register
0
1
read-write
IDR
Interrupt Disable Register
0x24
32
write-only
n
0x0
0x0
ACKDIS
Acknowledge Update Interrupt Disable
0
1
write-only
ALRDIS
Alarm Interrupt Disable
1
1
write-only
CALDIS
Calendar Event Interrupt Disable
4
1
write-only
SECDIS
Second Event Interrupt Disable
2
1
write-only
TDERRDIS
Time and/or Date Error Interrupt Disable
5
1
write-only
TIMDIS
Time Event Interrupt Disable
3
1
write-only
IER
Interrupt Enable Register
0x20
32
write-only
n
0x0
0x0
ACKEN
Acknowledge Update Interrupt Enable
0
1
write-only
ALREN
Alarm Interrupt Enable
1
1
write-only
CALEN
Calendar Event Interrupt Enable
4
1
write-only
SECEN
Second Event Interrupt Enable
2
1
write-only
TDERREN
Time and/or Date Error Interrupt Enable
5
1
write-only
TIMEN
Time Event Interrupt Enable
3
1
write-only
IMR
Interrupt Mask Register
0x28
32
read-only
n
0x0
0x0
ACK
Acknowledge Update Interrupt Mask
0
1
read-only
ALR
Alarm Interrupt Mask
1
1
read-only
CAL
Calendar Event Interrupt Mask
4
1
read-only
SEC
Second Event Interrupt Mask
2
1
read-only
TIM
Time Event Interrupt Mask
3
1
read-only
MR
Mode Register
0x4
32
read-write
n
0x0
0x0
CORRECTION
Slow Clock Correction
8
7
read-write
HIGHPPM
HIGH PPM Correction
15
1
read-write
HRMOD
12-/24-hour Mode
0
1
read-write
NEGPPM
NEGative PPM Correction
4
1
read-write
OUT0
RTCOUT0 OutputSource Selection
16
3
read-write
NO_WAVE
No waveform, stuck at '0'
0x0
FREQ1HZ
1 Hz square wave
0x1
FREQ32HZ
32 Hz square wave
0x2
FREQ64HZ
64 Hz square wave
0x3
FREQ512HZ
512 Hz square wave
0x4
ALARM_TOGGLE
Output toggles when alarm flag rises
0x5
ALARM_FLAG
Output is a copy of the alarm flag
0x6
PROG_PULSE
Duty cycle programmable pulse
0x7
PERSIAN
PERSIAN Calendar
1
1
read-write
THIGH
High Duration of the Output Pulse
24
3
read-write
H_31MS
31.2 ms
0x0
H_16MS
15.6 ms
0x1
H_4MS
3.91 ms
0x2
H_976US
976 us
0x3
H_488US
488 us
0x4
H_122US
122 us
0x5
H_30US
30.5 us
0x6
H_15US
15.2 us
0x7
TPERIOD
Period of the Output Pulse
28
2
read-write
P_1S
1 second
0x0
P_500MS
500 ms
0x1
P_250MS
250 ms
0x2
P_125MS
125 ms
0x3
SCCR
Status Clear Command Register
0x1C
32
write-only
n
0x0
0x0
ACKCLR
Acknowledge Clear
0
1
write-only
ALRCLR
Alarm Clear
1
1
write-only
CALCLR
Calendar Clear
4
1
write-only
SECCLR
Second Clear
2
1
write-only
TDERRCLR
Time and/or Date Free Running Error Clear
5
1
write-only
TIMCLR
Time Clear
3
1
write-only
SR
Status Register
0x18
32
read-only
n
0x0
0x0
ACKUPD
Acknowledge for Update
0
1
read-only
FREERUN
Time and calendar registers cannot be updated.
0
UPDATE
Time and calendar registers can be updated.
1
ALARM
Alarm Flag
1
1
read-only
NO_ALARMEVENT
No alarm matching condition occurred.
0
ALARMEVENT
An alarm matching condition has occurred.
1
CALEV
Calendar Event
4
1
read-only
NO_CALEVENT
No calendar event has occurred since the last clear.
0
CALEVENT
At least one calendar event has occurred since the last clear.
1
SEC
Second Event
2
1
read-only
NO_SECEVENT
No second event has occurred since the last clear.
0
SECEVENT
At least one second event has occurred since the last clear.
1
TDERR
Time and/or Date Free Running Error
5
1
read-only
CORRECT
The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR).
0
ERR_TIMEDATE
The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid.
1
TIMEV
Time Event
3
1
read-only
NO_TIMEVENT
No time event has occurred since the last clear.
0
TIMEVENT
At least one time event has occurred since the last clear.
1
TIMALR
Time Alarm Register
0x10
32
read-write
n
0x0
0x0
AMPM
AM/PM Indicator
22
1
read-write
HOUR
Hour Alarm
16
6
read-write
HOUREN
Hour Alarm Enable
23
1
read-write
MIN
Minute Alarm
8
7
read-write
MINEN
Minute Alarm Enable
15
1
read-write
SEC
Second Alarm
0
7
read-write
SECEN
Second Alarm Enable
7
1
read-write
TIMR
Time Register
0x8
32
read-write
n
0x0
0x0
AMPM
Ante Meridiem Post Meridiem Indicator
22
1
read-write
HOUR
Current Hour
16
6
read-write
MIN
Current Minute
8
7
read-write
SEC
Current Second
0
7
read-write
TSDR0
TimeStamp Date Register 0
0xB4
32
read-only
n
0x0
0x0
CENT
Century of the Tamper
0
7
read-only
DATE
Date of the Tamper
24
6
read-only
DAY
Day of the Tamper
21
3
read-only
MONTH
Month of the Tamper
16
5
read-only
YEAR
Year of the Tamper
8
8
read-only
TSDR1
TimeStamp Date Register 1
0xC0
32
read-only
n
0x0
0x0
CENT
Century of the Tamper
0
7
read-only
DATE
Date of the Tamper
24
6
read-only
DAY
Day of the Tamper
21
3
read-only
MONTH
Month of the Tamper
16
5
read-only
YEAR
Year of the Tamper
8
8
read-only
TSSR0
TimeStamp Source Register 0
0xB8
32
read-only
n
0x0
0x0
TSRC
Tamper Source
0
2
read-only
TSSR1
TimeStamp Source Register 1
0xC4
32
read-only
n
0x0
0x0
TSRC
Tamper Source
0
2
read-only
TSTR0
TimeStamp Time Register 0
0xB0
32
read-only
n
0x0
0x0
AMPM
AM/PM Indicator of the Tamper
22
1
read-only
BACKUP
System Mode of the Tamper
31
1
read-only
HOUR
Hours of the Tamper
16
6
read-only
MIN
Minutes of the Tamper
8
7
read-only
SEC
Seconds of the Tamper
0
7
read-only
TEVCNT
Tamper Events Counter
24
4
read-only
TSTR1
TimeStamp Time Register 1
0xBC
32
read-only
n
0x0
0x0
AMPM
AM/PM Indicator of the Tamper
22
1
read-only
BACKUP
System Mode of the Tamper
31
1
read-only
HOUR
Hours of the Tamper
16
6
read-only
MIN
Minutes of the Tamper
8
7
read-only
SEC
Seconds of the Tamper
0
7
read-only
VER
Valid Entry Register
0x2C
32
read-only
n
0x0
0x0
NVCAL
Non-valid Calendar
1
1
read-only
NVCALALR
Non-valid Calendar Alarm
3
1
read-only
NVTIM
Non-valid Time
0
1
read-only
NVTIMALR
Non-valid Time Alarm
2
1
read-only
WPMR
Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protection Enable
0
1
read-write
WPKEY
Write Protection Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
0x525443
RTT
Real-time Timer
SYSC
0x0
0x0
0x200
registers
n
AR
Alarm Register
0x4
32
read-write
n
0x0
0x0
ALMV
Alarm Value
0
32
read-write
MR
Mode Register
0x0
32
read-write
n
0x0
0x0
ALMIEN
Alarm Interrupt Enable
16
1
read-write
RTC1HZ
Real-Time Clock 1Hz Clock Selection
24
1
read-write
RTPRES
Real-time Timer Prescaler Value
0
16
read-write
RTTDIS
Real-time Timer Disable
20
1
read-write
RTTINCIEN
Real-time Timer Increment Interrupt Enable
17
1
read-write
RTTRST
Real-time Timer Restart
18
1
read-write
SR
Status Register
0xC
32
read-only
n
0x0
0x0
ALMS
Real-time Alarm Status
0
1
read-only
RTTINC
Prescaler Roll-over Status
1
1
read-only
VR
Value Register
0x8
32
read-only
n
0x0
0x0
CRTV
Current Real-time Value
0
32
read-only
SLCDC
Segment LCD Controller
SLCDC
0x0
0x0
0x50
registers
n
SLCDC
32
CR
SLCDC Control Register
0x0
32
write-only
n
0x0
0x0
LCDDIS
Disable LCDC
1
1
write-only
LCDEN
Enable the LCDC
0
1
write-only
SWRST
Software Reset
3
1
write-only
DR
SLCDC Display Register
0xC
32
read-write
n
0x0
0x0
DISPMODE
Display Mode Register
0
3
read-write
NORMAL
Normal Mode-Latched data are displayed.
0x0
FORCE_OFF
Force Off Mode-All pixels are invisible. (The SLCDC memory is unchanged.)
0x1
FORCE_ON
Force On Mode-All pixels are visible. (The SLCDC memory is unchanged.)
0x2
BLINKING
Blinking Mode-All pixels are alternately turned off to the predefined state in SLCDC memory at LCDBLKFREQ frequency. (The SLCDC memory is unchanged.)
0x3
INVERTED
Inverted Mode-All pixels are set in the inverted state as defined in SLCDC memory. (The SLCDC memory is unchanged.)
0x4
INVERTED_BLINK
Inverted Blinking Mode-All pixels are alternately turned off to the predefined opposite state in SLCDC memory at LCDBLKFREQ frequency. (The SLCDC memory is unchanged.)
0x5
USER_BUFFER_LOAD
User Buffer Only Load Mode-Blocks the automatic transfer from User Buffer to Display Buffer.
0x6
BUFFERS_SWAP
Buffer Swap Mode-All pixels are alternatively assigned to the state defined in the User Buffer, then to the state defined in the Display Buffer at LCDBLKFREQ frequency.
0x7
LCDBLKFREQ
LCD Blinking Frequency Selection
8
8
read-write
FRR
SLCDC Frame Rate Register
0x8
32
read-write
n
0x0
0x0
DIV
Clock Division
8
3
read-write
PRESC_CLK_DIV1
Clock output from prescaler is divided by 1
0x0
PRESC_CLK_DIV2
Clock output from prescaler is divided by 2
0x1
PRESC_CLK_DIV3
Clock output from prescaler is divided by 3
0x2
PRESC_CLK_DIV4
Clock output from prescaler is divided by 4
0x3
PRESC_CLK_DIV5
Clock output from prescaler is divided by 5
0x4
PRESC_CLK_DIV6
Clock output from prescaler is divided by 6
0x5
PRESC_CLK_DIV7
Clock output from prescaler is divided by 7
0x6
PRESC_CLK_DIV8
Clock output from prescaler is divided by 8
0x7
PRESC
Clock Prescaler
0
3
read-write
SLCK_DIV8
Slow clock is divided by 8
0x0
SLCK_DIV16
Slow clock is divided by 16
0x1
SLCK_DIV32
Slow clock is divided by 32
0x2
SLCK_DIV64
Slow clock is divided by 64
0x3
SLCK_DIV128
Slow clock is divided by 128
0x4
SLCK_DIV256
Slow clock is divided by 256
0x5
SLCK_DIV512
Slow clock is divided by 512
0x6
SLCK_DIV1024
Slow clock is divided by 1024
0x7
IDR
SLCDC Interrupt Disable Register
0x24
32
write-only
n
0x0
0x0
DIS
SLCDC Disable Completion Interrupt Disable
2
1
write-only
ENDFRAME
End of Frame Interrupt Disable
0
1
write-only
IER
SLCDC Interrupt Enable Register
0x20
32
write-only
n
0x0
0x0
DIS
SLCDC Disable Completion Interrupt Enable
2
1
write-only
ENDFRAME
End of Frame Interrupt Enable
0
1
write-only
IMR
SLCDC Interrupt Mask Register
0x28
32
read-only
n
0x0
0x0
DIS
SLCDC Disable Completion Interrupt Mask
2
1
read-only
ENDFRAME
End of Frame Interrupt Mask
0
1
read-only
ISR
SLCDC Interrupt Status Register
0x2C
32
read-only
n
0x0
0x0
DIS
SLCDC Disable Completion Interrupt Status
2
1
read-only
ENDFRAME
End of Frame Interrupt Status
0
1
read-only
LMEMR0
SLCDC LSB Memory Register (com = 0)
0x200
32
read-write
n
0x0
0x0
LPIXEL
LSB Pixels pattern associated to COMx terminal
0
32
read-write
LMEMR1
SLCDC LSB Memory Register (com = 1)
0x208
32
read-write
n
0x0
0x0
LPIXEL
LSB Pixels pattern associated to COMx terminal
0
32
read-write
LMEMR2
SLCDC LSB Memory Register (com = 2)
0x210
32
read-write
n
0x0
0x0
LPIXEL
LSB Pixels pattern associated to COMx terminal
0
32
read-write
LMEMR3
SLCDC LSB Memory Register (com = 3)
0x218
32
read-write
n
0x0
0x0
LPIXEL
LSB Pixels pattern associated to COMx terminal
0
32
read-write
LMEMR4
SLCDC LSB Memory Register (com = 4)
0x220
32
read-write
n
0x0
0x0
LPIXEL
LSB Pixels pattern associated to COMx terminal
0
32
read-write
LMEMR5
SLCDC LSB Memory Register (com = 5)
0x228
32
read-write
n
0x0
0x0
LPIXEL
LSB Pixels pattern associated to COMx terminal
0
32
read-write
MMEMR0
SLCDC MSB Memory Register (com = 0)
0x204
32
read-write
n
0x0
0x0
MPIXEL
MSB Pixels pattern associated to COMx terminal
0
32
read-write
MMEMR1
SLCDC MSB Memory Register (com = 1)
0x20C
32
read-write
n
0x0
0x0
MPIXEL
MSB Pixels pattern associated to COMx terminal
0
32
read-write
MMEMR2
SLCDC MSB Memory Register (com = 2)
0x214
32
read-write
n
0x0
0x0
MPIXEL
MSB Pixels pattern associated to COMx terminal
0
32
read-write
MMEMR3
SLCDC MSB Memory Register (com = 3)
0x21C
32
read-write
n
0x0
0x0
MPIXEL
MSB Pixels pattern associated to COMx terminal
0
32
read-write
MMEMR4
SLCDC MSB Memory Register (com = 4)
0x224
32
read-write
n
0x0
0x0
MPIXEL
MSB Pixels pattern associated to COMx terminal
0
32
read-write
MMEMR5
SLCDC MSB Memory Register (com = 5)
0x22C
32
read-write
n
0x0
0x0
MPIXEL
MSB Pixels pattern associated to COMx terminal
0
32
read-write
MR
SLCDC Mode Register
0x4
32
read-write
n
0x0
0x0
BIAS
LCD Display Configuration
20
2
read-write
STATIC
Static
0x0
BIAS_1_2
Bias 1/2
0x1
BIAS_1_3
Bias 1/3
0x2
BUFTIME
Buffer On-Time
16
4
read-write
OFF
Nominal drive time is 0% of SLCK period
0x0
X2_SLCK_PERIOD
Nominal drive time is 2 periods of SLCK clock
0x1
X4_SLCK_PERIOD
Nominal drive time is 4 periods of SLCK clock
0x2
X8_SLCK_PERIOD
Nominal drive time is 8 periods of SLCK clock
0x3
X16_SLCK_PERIOD
Nominal drive time is 16 periods of SLCK clock
0x4
X32_SLCK_PERIOD
Nominal drive time is 32 periods of SLCK clock
0x5
X64_SLCK_PERIOD
Nominal drive time is 64 periods of SLCK clock
0x6
X128_SLCK_PERIOD
Nominal drive time is 128 periods of SLCK clock
0x7
PERCENT_50
Nominal drive time is 50% of SLCK period
0x8
PERCENT_100
Nominal drive time is 100% of SLCK period
0x9
COMSEL
Selection of the Number of Commons
0
3
read-write
COM_0
COM0 is driven by SLCDC, COM1:5 are driven by digital function
0x0
COM_0TO1
COM0:1 are driven by SLCDC, COM2:5 are driven by digital function
0x1
COM_0TO2
COM0:2 are driven by SLCDC, COM3:5 are driven by digital function
0x2
COM_0TO3
COM0:3 are driven by SLCDC, COM4:5 are driven by digital function
0x3
COM_0TO4
COM0:4 are driven by SLCDC, COM5 is driven by digital function
0x4
COM_0TO5
COM0:5 are driven by SLCDC, No COM pin driven by digital function
0x5
LPMODE
Low Power Mode
24
1
read-write
SEGSEL
Selection of the Number of Segments
8
6
read-write
SMR0
SLCDC Segment Map Register 0
0x30
32
read-write
n
0x0
0x0
LCD0
LCD Segment Mapped on SEGx I/O Pin
0
1
read-write
LCD1
LCD Segment Mapped on SEGx I/O Pin
1
1
read-write
LCD10
LCD Segment Mapped on SEGx I/O Pin
10
1
read-write
LCD11
LCD Segment Mapped on SEGx I/O Pin
11
1
read-write
LCD12
LCD Segment Mapped on SEGx I/O Pin
12
1
read-write
LCD13
LCD Segment Mapped on SEGx I/O Pin
13
1
read-write
LCD14
LCD Segment Mapped on SEGx I/O Pin
14
1
read-write
LCD15
LCD Segment Mapped on SEGx I/O Pin
15
1
read-write
LCD16
LCD Segment Mapped on SEGx I/O Pin
16
1
read-write
LCD17
LCD Segment Mapped on SEGx I/O Pin
17
1
read-write
LCD18
LCD Segment Mapped on SEGx I/O Pin
18
1
read-write
LCD19
LCD Segment Mapped on SEGx I/O Pin
19
1
read-write
LCD2
LCD Segment Mapped on SEGx I/O Pin
2
1
read-write
LCD20
LCD Segment Mapped on SEGx I/O Pin
20
1
read-write
LCD21
LCD Segment Mapped on SEGx I/O Pin
21
1
read-write
LCD22
LCD Segment Mapped on SEGx I/O Pin
22
1
read-write
LCD23
LCD Segment Mapped on SEGx I/O Pin
23
1
read-write
LCD24
LCD Segment Mapped on SEGx I/O Pin
24
1
read-write
LCD25
LCD Segment Mapped on SEGx I/O Pin
25
1
read-write
LCD26
LCD Segment Mapped on SEGx I/O Pin
26
1
read-write
LCD27
LCD Segment Mapped on SEGx I/O Pin
27
1
read-write
LCD28
LCD Segment Mapped on SEGx I/O Pin
28
1
read-write
LCD29
LCD Segment Mapped on SEGx I/O Pin
29
1
read-write
LCD3
LCD Segment Mapped on SEGx I/O Pin
3
1
read-write
LCD30
LCD Segment Mapped on SEGx I/O Pin
30
1
read-write
LCD31
LCD Segment Mapped on SEGx I/O Pin
31
1
read-write
LCD4
LCD Segment Mapped on SEGx I/O Pin
4
1
read-write
LCD5
LCD Segment Mapped on SEGx I/O Pin
5
1
read-write
LCD6
LCD Segment Mapped on SEGx I/O Pin
6
1
read-write
LCD7
LCD Segment Mapped on SEGx I/O Pin
7
1
read-write
LCD8
LCD Segment Mapped on SEGx I/O Pin
8
1
read-write
LCD9
LCD Segment Mapped on SEGx I/O Pin
9
1
read-write
SMR1
SLCDC Segment Map Register 1
0x34
32
read-write
n
0x0
0x0
LCD32
LCD Segment Mapped on SEGx I/O Pin
0
1
read-write
LCD33
LCD Segment Mapped on SEGx I/O Pin
1
1
read-write
LCD34
LCD Segment Mapped on SEGx I/O Pin
2
1
read-write
LCD35
LCD Segment Mapped on SEGx I/O Pin
3
1
read-write
LCD36
LCD Segment Mapped on SEGx I/O Pin
4
1
read-write
LCD37
LCD Segment Mapped on SEGx I/O Pin
5
1
read-write
LCD38
LCD Segment Mapped on SEGx I/O Pin
6
1
read-write
LCD39
LCD Segment Mapped on SEGx I/O Pin
7
1
read-write
LCD40
LCD Segment Mapped on SEGx I/O Pin
8
1
read-write
LCD41
LCD Segment Mapped on SEGx I/O Pin
9
1
read-write
LCD42
LCD Segment Mapped on SEGx I/O Pin
10
1
read-write
LCD43
LCD Segment Mapped on SEGx I/O Pin
11
1
read-write
LCD44
LCD Segment Mapped on SEGx I/O Pin
12
1
read-write
LCD45
LCD Segment Mapped on SEGx I/O Pin
13
1
read-write
LCD46
LCD Segment Mapped on SEGx I/O Pin
14
1
read-write
LCD47
LCD Segment Mapped on SEGx I/O Pin
15
1
read-write
LCD48
LCD Segment Mapped on SEGx I/O Pin
16
1
read-write
LCD49
LCD Segment Mapped on SEGx I/O Pin
17
1
read-write
SR
SLCDC Status Register
0x10
32
read-only
n
0x0
0x0
ENA
Enable Status (Automatically Set/Reset)
0
1
read-only
WPMR
SLCDC Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protection Enable
0
1
read-write
WPKEY
Write Protection Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
0x4C4344
WPSR
SLCDC Write Protection Status Register
0xE8
32
read-only
n
0x0
0x0
WPVS
Write Protection Violation Status
0
1
read-only
WPVSRC
Write Protection Violation Source
8
16
read-only
SMC0
Static Memory Controller 0
SMC
0x0
0x0
0x200
registers
n
CYCLE0
SMC Cycle Register (CS_number = 0)
0x8
32
read-write
n
0x0
0x0
NRD_CYCLE
Total Read Cycle Length
16
9
read-write
NWE_CYCLE
Total Write Cycle Length
0
9
read-write
CYCLE1
SMC Cycle Register (CS_number = 1)
0x18
32
read-write
n
0x0
0x0
NRD_CYCLE
Total Read Cycle Length
16
9
read-write
NWE_CYCLE
Total Write Cycle Length
0
9
read-write
CYCLE2
SMC Cycle Register (CS_number = 2)
0x28
32
read-write
n
0x0
0x0
NRD_CYCLE
Total Read Cycle Length
16
9
read-write
NWE_CYCLE
Total Write Cycle Length
0
9
read-write
CYCLE3
SMC Cycle Register (CS_number = 3)
0x38
32
read-write
n
0x0
0x0
NRD_CYCLE
Total Read Cycle Length
16
9
read-write
NWE_CYCLE
Total Write Cycle Length
0
9
read-write
KEY1
SMC OCMS KEY1 Register
0x84
32
write-only
n
0x0
0x0
KEY1
Off Chip Memory Scrambling (OCMS) Key Part 1
0
32
write-only
KEY2
SMC OCMS KEY2 Register
0x88
32
write-only
n
0x0
0x0
KEY2
Off Chip Memory Scrambling (OCMS) Key Part 2
0
32
write-only
MODE0
SMC Mode Register (CS_number = 0)
0xC
32
read-write
n
0x0
0x0
BAT
Byte Access Type
8
1
read-write
BYTE_SELECT
Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
0
BYTE_WRITE
Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
1
DBW
Data Bus Width
12
1
read-write
8_BIT
8-bit Data Bus
0
16_BIT
16-bit Data Bus
1
EXNW_MODE
NWAIT Mode
4
2
read-write
DISABLED
Disabled
0x0
FROZEN
Frozen Mode
0x2
READY
Ready Mode
0x3
PMEN
Page Mode Enabled
24
1
read-write
PS
Page Size
28
2
read-write
4_BYTE
4-byte page
0x0
8_BYTE
8-byte page
0x1
16_BYTE
16-byte page
0x2
32_BYTE
32-byte page
0x3
READ_MODE
Read Mode
0
1
read-write
TDF_CYCLES
Data Float Time
16
4
read-write
TDF_MODE
TDF Optimization
20
1
read-write
WRITE_MODE
Write Mode
1
1
read-write
MODE1
SMC Mode Register (CS_number = 1)
0x1C
32
read-write
n
0x0
0x0
BAT
Byte Access Type
8
1
read-write
BYTE_SELECT
Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
0
BYTE_WRITE
Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
1
DBW
Data Bus Width
12
1
read-write
8_BIT
8-bit Data Bus
0
16_BIT
16-bit Data Bus
1
EXNW_MODE
NWAIT Mode
4
2
read-write
DISABLED
Disabled
0x0
FROZEN
Frozen Mode
0x2
READY
Ready Mode
0x3
PMEN
Page Mode Enabled
24
1
read-write
PS
Page Size
28
2
read-write
4_BYTE
4-byte page
0x0
8_BYTE
8-byte page
0x1
16_BYTE
16-byte page
0x2
32_BYTE
32-byte page
0x3
READ_MODE
Read Mode
0
1
read-write
TDF_CYCLES
Data Float Time
16
4
read-write
TDF_MODE
TDF Optimization
20
1
read-write
WRITE_MODE
Write Mode
1
1
read-write
MODE2
SMC Mode Register (CS_number = 2)
0x2C
32
read-write
n
0x0
0x0
BAT
Byte Access Type
8
1
read-write
BYTE_SELECT
Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
0
BYTE_WRITE
Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
1
DBW
Data Bus Width
12
1
read-write
8_BIT
8-bit Data Bus
0
16_BIT
16-bit Data Bus
1
EXNW_MODE
NWAIT Mode
4
2
read-write
DISABLED
Disabled
0x0
FROZEN
Frozen Mode
0x2
READY
Ready Mode
0x3
PMEN
Page Mode Enabled
24
1
read-write
PS
Page Size
28
2
read-write
4_BYTE
4-byte page
0x0
8_BYTE
8-byte page
0x1
16_BYTE
16-byte page
0x2
32_BYTE
32-byte page
0x3
READ_MODE
Read Mode
0
1
read-write
TDF_CYCLES
Data Float Time
16
4
read-write
TDF_MODE
TDF Optimization
20
1
read-write
WRITE_MODE
Write Mode
1
1
read-write
MODE3
SMC Mode Register (CS_number = 3)
0x3C
32
read-write
n
0x0
0x0
BAT
Byte Access Type
8
1
read-write
BYTE_SELECT
Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
0
BYTE_WRITE
Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
1
DBW
Data Bus Width
12
1
read-write
8_BIT
8-bit Data Bus
0
16_BIT
16-bit Data Bus
1
EXNW_MODE
NWAIT Mode
4
2
read-write
DISABLED
Disabled
0x0
FROZEN
Frozen Mode
0x2
READY
Ready Mode
0x3
PMEN
Page Mode Enabled
24
1
read-write
PS
Page Size
28
2
read-write
4_BYTE
4-byte page
0x0
8_BYTE
8-byte page
0x1
16_BYTE
16-byte page
0x2
32_BYTE
32-byte page
0x3
READ_MODE
Read Mode
0
1
read-write
TDF_CYCLES
Data Float Time
16
4
read-write
TDF_MODE
TDF Optimization
20
1
read-write
WRITE_MODE
Write Mode
1
1
read-write
OCMS
SMC OCMS MODE Register
0x80
32
read-write
n
0x0
0x0
CS0SE
Chip Select (x = 0 to 3) Scrambling Enable
16
1
read-write
CS1SE
Chip Select (x = 0 to 3) Scrambling Enable
17
1
read-write
CS2SE
Chip Select (x = 0 to 3) Scrambling Enable
18
1
read-write
CS3SE
Chip Select (x = 0 to 3) Scrambling Enable
19
1
read-write
SMSE
Static Memory Controller Scrambling EnableSAM4C0x00030003CS0SECS1SECS1SECS2SECS3SE
0
1
read-write
PULSE0
SMC Pulse Register (CS_number = 0)
0x4
32
read-write
n
0x0
0x0
NCS_RD_PULSE
NCS Pulse Length in READ Access
24
7
read-write
NCS_WR_PULSE
NCS Pulse Length in WRITE Access
8
7
read-write
NRD_PULSE
NRD Pulse Length
16
7
read-write
NWE_PULSE
NWE Pulse Length
0
7
read-write
PULSE1
SMC Pulse Register (CS_number = 1)
0x14
32
read-write
n
0x0
0x0
NCS_RD_PULSE
NCS Pulse Length in READ Access
24
7
read-write
NCS_WR_PULSE
NCS Pulse Length in WRITE Access
8
7
read-write
NRD_PULSE
NRD Pulse Length
16
7
read-write
NWE_PULSE
NWE Pulse Length
0
7
read-write
PULSE2
SMC Pulse Register (CS_number = 2)
0x24
32
read-write
n
0x0
0x0
NCS_RD_PULSE
NCS Pulse Length in READ Access
24
7
read-write
NCS_WR_PULSE
NCS Pulse Length in WRITE Access
8
7
read-write
NRD_PULSE
NRD Pulse Length
16
7
read-write
NWE_PULSE
NWE Pulse Length
0
7
read-write
PULSE3
SMC Pulse Register (CS_number = 3)
0x34
32
read-write
n
0x0
0x0
NCS_RD_PULSE
NCS Pulse Length in READ Access
24
7
read-write
NCS_WR_PULSE
NCS Pulse Length in WRITE Access
8
7
read-write
NRD_PULSE
NRD Pulse Length
16
7
read-write
NWE_PULSE
NWE Pulse Length
0
7
read-write
SETUP0
SMC Setup Register (CS_number = 0)
0x0
32
read-write
n
0x0
0x0
NCS_RD_SETUP
NCS Setup Length in READ Access
24
6
read-write
NCS_WR_SETUP
NCS Setup Length in WRITE Access
8
6
read-write
NRD_SETUP
NRD Setup Length
16
6
read-write
NWE_SETUP
NWE Setup Length
0
6
read-write
SETUP1
SMC Setup Register (CS_number = 1)
0x10
32
read-write
n
0x0
0x0
NCS_RD_SETUP
NCS Setup Length in READ Access
24
6
read-write
NCS_WR_SETUP
NCS Setup Length in WRITE Access
8
6
read-write
NRD_SETUP
NRD Setup Length
16
6
read-write
NWE_SETUP
NWE Setup Length
0
6
read-write
SETUP2
SMC Setup Register (CS_number = 2)
0x20
32
read-write
n
0x0
0x0
NCS_RD_SETUP
NCS Setup Length in READ Access
24
6
read-write
NCS_WR_SETUP
NCS Setup Length in WRITE Access
8
6
read-write
NRD_SETUP
NRD Setup Length
16
6
read-write
NWE_SETUP
NWE Setup Length
0
6
read-write
SETUP3
SMC Setup Register (CS_number = 3)
0x30
32
read-write
n
0x0
0x0
NCS_RD_SETUP
NCS Setup Length in READ Access
24
6
read-write
NCS_WR_SETUP
NCS Setup Length in WRITE Access
8
6
read-write
NRD_SETUP
NRD Setup Length
16
6
read-write
NWE_SETUP
NWE Setup Length
0
6
read-write
WPMR
SMC Write Protect Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protect Enable
0
1
read-write
WPKEY
Write Protect KEY
8
24
read-write
WPSR
SMC Write Protect Status Register
0xE8
32
read-only
n
0x0
0x0
WPVS
Write Protect Enable
0
1
read-only
WPVSRC
Write Protect Violation Source
8
16
read-only
SMC1
Static Memory Controller 1
SMC
0x0
0x0
0x50
registers
n
CYCLE0
SMC Cycle Register (CS_number = 0)
0x8
32
read-write
n
0x0
0x0
NRD_CYCLE
Total Read Cycle Length
16
9
read-write
NWE_CYCLE
Total Write Cycle Length
0
9
read-write
CYCLE1
SMC Cycle Register (CS_number = 1)
0x18
32
read-write
n
0x0
0x0
NRD_CYCLE
Total Read Cycle Length
16
9
read-write
NWE_CYCLE
Total Write Cycle Length
0
9
read-write
CYCLE2
SMC Cycle Register (CS_number = 2)
0x28
32
read-write
n
0x0
0x0
NRD_CYCLE
Total Read Cycle Length
16
9
read-write
NWE_CYCLE
Total Write Cycle Length
0
9
read-write
CYCLE3
SMC Cycle Register (CS_number = 3)
0x38
32
read-write
n
0x0
0x0
NRD_CYCLE
Total Read Cycle Length
16
9
read-write
NWE_CYCLE
Total Write Cycle Length
0
9
read-write
KEY1
SMC OCMS KEY1 Register
0x84
32
write-only
n
0x0
0x0
KEY1
Off Chip Memory Scrambling (OCMS) Key Part 1
0
32
write-only
KEY2
SMC OCMS KEY2 Register
0x88
32
write-only
n
0x0
0x0
KEY2
Off Chip Memory Scrambling (OCMS) Key Part 2
0
32
write-only
MODE0
SMC Mode Register (CS_number = 0)
0xC
32
read-write
n
0x0
0x0
BAT
Byte Access Type
8
1
read-write
BYTE_SELECT
Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
0
BYTE_WRITE
Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
1
DBW
Data Bus Width
12
1
read-write
8_BIT
8-bit Data Bus
0
16_BIT
16-bit Data Bus
1
EXNW_MODE
NWAIT Mode
4
2
read-write
DISABLED
Disabled
0x0
FROZEN
Frozen Mode
0x2
READY
Ready Mode
0x3
PMEN
Page Mode Enabled
24
1
read-write
PS
Page Size
28
2
read-write
4_BYTE
4-byte page
0x0
8_BYTE
8-byte page
0x1
16_BYTE
16-byte page
0x2
32_BYTE
32-byte page
0x3
READ_MODE
Read Mode
0
1
read-write
TDF_CYCLES
Data Float Time
16
4
read-write
TDF_MODE
TDF Optimization
20
1
read-write
WRITE_MODE
Write Mode
1
1
read-write
MODE1
SMC Mode Register (CS_number = 1)
0x1C
32
read-write
n
0x0
0x0
BAT
Byte Access Type
8
1
read-write
BYTE_SELECT
Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
0
BYTE_WRITE
Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
1
DBW
Data Bus Width
12
1
read-write
8_BIT
8-bit Data Bus
0
16_BIT
16-bit Data Bus
1
EXNW_MODE
NWAIT Mode
4
2
read-write
DISABLED
Disabled
0x0
FROZEN
Frozen Mode
0x2
READY
Ready Mode
0x3
PMEN
Page Mode Enabled
24
1
read-write
PS
Page Size
28
2
read-write
4_BYTE
4-byte page
0x0
8_BYTE
8-byte page
0x1
16_BYTE
16-byte page
0x2
32_BYTE
32-byte page
0x3
READ_MODE
Read Mode
0
1
read-write
TDF_CYCLES
Data Float Time
16
4
read-write
TDF_MODE
TDF Optimization
20
1
read-write
WRITE_MODE
Write Mode
1
1
read-write
MODE2
SMC Mode Register (CS_number = 2)
0x2C
32
read-write
n
0x0
0x0
BAT
Byte Access Type
8
1
read-write
BYTE_SELECT
Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
0
BYTE_WRITE
Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
1
DBW
Data Bus Width
12
1
read-write
8_BIT
8-bit Data Bus
0
16_BIT
16-bit Data Bus
1
EXNW_MODE
NWAIT Mode
4
2
read-write
DISABLED
Disabled
0x0
FROZEN
Frozen Mode
0x2
READY
Ready Mode
0x3
PMEN
Page Mode Enabled
24
1
read-write
PS
Page Size
28
2
read-write
4_BYTE
4-byte page
0x0
8_BYTE
8-byte page
0x1
16_BYTE
16-byte page
0x2
32_BYTE
32-byte page
0x3
READ_MODE
Read Mode
0
1
read-write
TDF_CYCLES
Data Float Time
16
4
read-write
TDF_MODE
TDF Optimization
20
1
read-write
WRITE_MODE
Write Mode
1
1
read-write
MODE3
SMC Mode Register (CS_number = 3)
0x3C
32
read-write
n
0x0
0x0
BAT
Byte Access Type
8
1
read-write
BYTE_SELECT
Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
0
BYTE_WRITE
Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
1
DBW
Data Bus Width
12
1
read-write
8_BIT
8-bit Data Bus
0
16_BIT
16-bit Data Bus
1
EXNW_MODE
NWAIT Mode
4
2
read-write
DISABLED
Disabled
0x0
FROZEN
Frozen Mode
0x2
READY
Ready Mode
0x3
PMEN
Page Mode Enabled
24
1
read-write
PS
Page Size
28
2
read-write
4_BYTE
4-byte page
0x0
8_BYTE
8-byte page
0x1
16_BYTE
16-byte page
0x2
32_BYTE
32-byte page
0x3
READ_MODE
Read Mode
0
1
read-write
TDF_CYCLES
Data Float Time
16
4
read-write
TDF_MODE
TDF Optimization
20
1
read-write
WRITE_MODE
Write Mode
1
1
read-write
OCMS
SMC OCMS MODE Register
0x80
32
read-write
n
0x0
0x0
CS0SE
Chip Select (x = 0 to 3) Scrambling Enable
16
1
read-write
CS1SE
Chip Select (x = 0 to 3) Scrambling Enable
17
1
read-write
CS2SE
Chip Select (x = 0 to 3) Scrambling Enable
18
1
read-write
CS3SE
Chip Select (x = 0 to 3) Scrambling Enable
19
1
read-write
SMSE
Static Memory Controller Scrambling EnableSAM4C0x00030003CS0SECS1SECS1SECS2SECS3SE
0
1
read-write
PULSE0
SMC Pulse Register (CS_number = 0)
0x4
32
read-write
n
0x0
0x0
NCS_RD_PULSE
NCS Pulse Length in READ Access
24
7
read-write
NCS_WR_PULSE
NCS Pulse Length in WRITE Access
8
7
read-write
NRD_PULSE
NRD Pulse Length
16
7
read-write
NWE_PULSE
NWE Pulse Length
0
7
read-write
PULSE1
SMC Pulse Register (CS_number = 1)
0x14
32
read-write
n
0x0
0x0
NCS_RD_PULSE
NCS Pulse Length in READ Access
24
7
read-write
NCS_WR_PULSE
NCS Pulse Length in WRITE Access
8
7
read-write
NRD_PULSE
NRD Pulse Length
16
7
read-write
NWE_PULSE
NWE Pulse Length
0
7
read-write
PULSE2
SMC Pulse Register (CS_number = 2)
0x24
32
read-write
n
0x0
0x0
NCS_RD_PULSE
NCS Pulse Length in READ Access
24
7
read-write
NCS_WR_PULSE
NCS Pulse Length in WRITE Access
8
7
read-write
NRD_PULSE
NRD Pulse Length
16
7
read-write
NWE_PULSE
NWE Pulse Length
0
7
read-write
PULSE3
SMC Pulse Register (CS_number = 3)
0x34
32
read-write
n
0x0
0x0
NCS_RD_PULSE
NCS Pulse Length in READ Access
24
7
read-write
NCS_WR_PULSE
NCS Pulse Length in WRITE Access
8
7
read-write
NRD_PULSE
NRD Pulse Length
16
7
read-write
NWE_PULSE
NWE Pulse Length
0
7
read-write
SETUP0
SMC Setup Register (CS_number = 0)
0x0
32
read-write
n
0x0
0x0
NCS_RD_SETUP
NCS Setup Length in READ Access
24
6
read-write
NCS_WR_SETUP
NCS Setup Length in WRITE Access
8
6
read-write
NRD_SETUP
NRD Setup Length
16
6
read-write
NWE_SETUP
NWE Setup Length
0
6
read-write
SETUP1
SMC Setup Register (CS_number = 1)
0x10
32
read-write
n
0x0
0x0
NCS_RD_SETUP
NCS Setup Length in READ Access
24
6
read-write
NCS_WR_SETUP
NCS Setup Length in WRITE Access
8
6
read-write
NRD_SETUP
NRD Setup Length
16
6
read-write
NWE_SETUP
NWE Setup Length
0
6
read-write
SETUP2
SMC Setup Register (CS_number = 2)
0x20
32
read-write
n
0x0
0x0
NCS_RD_SETUP
NCS Setup Length in READ Access
24
6
read-write
NCS_WR_SETUP
NCS Setup Length in WRITE Access
8
6
read-write
NRD_SETUP
NRD Setup Length
16
6
read-write
NWE_SETUP
NWE Setup Length
0
6
read-write
SETUP3
SMC Setup Register (CS_number = 3)
0x30
32
read-write
n
0x0
0x0
NCS_RD_SETUP
NCS Setup Length in READ Access
24
6
read-write
NCS_WR_SETUP
NCS Setup Length in WRITE Access
8
6
read-write
NRD_SETUP
NRD Setup Length
16
6
read-write
NWE_SETUP
NWE Setup Length
0
6
read-write
WPMR
SMC Write Protect Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protect Enable
0
1
read-write
WPKEY
Write Protect KEY
8
24
read-write
WPSR
SMC Write Protect Status Register
0xE8
32
read-only
n
0x0
0x0
WPVS
Write Protect Enable
0
1
read-only
WPVSRC
Write Protect Violation Source
8
16
read-only
SPI0
Serial Peripheral Interface 0
SPI
0x0
0x0
0x50
registers
n
SPI0
21
CR
Control Register
0x0
32
write-only
n
0x0
0x0
LASTXFER
Last Transfer
24
1
write-only
SPIDIS
SPI Disable
1
1
write-only
SPIEN
SPI Enable
0
1
write-only
SWRST
SPI Software Reset
7
1
write-only
CSR0
Chip Select Register
0x30
32
read-write
n
BITS
Bits Per Transfer
4
4
read-write
8_BIT
8 bits for transfer
0x0
9_BIT
9 bits for transfer
0x1
10_BIT
10 bits for transfer
0x2
11_BIT
11 bits for transfer
0x3
12_BIT
12 bits for transfer
0x4
13_BIT
13 bits for transfer
0x5
14_BIT
14 bits for transfer
0x6
15_BIT
15 bits for transfer
0x7
16_BIT
16 bits for transfer
0x8
CPOL
Clock Polarity
0
1
read-write
CSAAT
Chip Select Active After Transfer
3
1
read-write
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
read-write
DLYBCT
Delay Between Consecutive Transfers
24
8
read-write
DLYBS
Delay Before SPCK
16
8
read-write
NCPHA
Clock Phase
1
1
read-write
SCBR
Serial Clock Baud Rate
8
8
read-write
CSR1
Chip Select Register
0x34
32
read-write
n
BITS
Bits Per Transfer
4
4
read-write
8_BIT
8 bits for transfer
0x0
9_BIT
9 bits for transfer
0x1
10_BIT
10 bits for transfer
0x2
11_BIT
11 bits for transfer
0x3
12_BIT
12 bits for transfer
0x4
13_BIT
13 bits for transfer
0x5
14_BIT
14 bits for transfer
0x6
15_BIT
15 bits for transfer
0x7
16_BIT
16 bits for transfer
0x8
CPOL
Clock Polarity
0
1
read-write
CSAAT
Chip Select Active After Transfer
3
1
read-write
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
read-write
DLYBCT
Delay Between Consecutive Transfers
24
8
read-write
DLYBS
Delay Before SPCK
16
8
read-write
NCPHA
Clock Phase
1
1
read-write
SCBR
Serial Clock Baud Rate
8
8
read-write
CSR2
Chip Select Register
0x38
32
read-write
n
BITS
Bits Per Transfer
4
4
read-write
8_BIT
8 bits for transfer
0x0
9_BIT
9 bits for transfer
0x1
10_BIT
10 bits for transfer
0x2
11_BIT
11 bits for transfer
0x3
12_BIT
12 bits for transfer
0x4
13_BIT
13 bits for transfer
0x5
14_BIT
14 bits for transfer
0x6
15_BIT
15 bits for transfer
0x7
16_BIT
16 bits for transfer
0x8
CPOL
Clock Polarity
0
1
read-write
CSAAT
Chip Select Active After Transfer
3
1
read-write
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
read-write
DLYBCT
Delay Between Consecutive Transfers
24
8
read-write
DLYBS
Delay Before SPCK
16
8
read-write
NCPHA
Clock Phase
1
1
read-write
SCBR
Serial Clock Baud Rate
8
8
read-write
CSR3
Chip Select Register
0x3C
32
read-write
n
BITS
Bits Per Transfer
4
4
read-write
8_BIT
8 bits for transfer
0x0
9_BIT
9 bits for transfer
0x1
10_BIT
10 bits for transfer
0x2
11_BIT
11 bits for transfer
0x3
12_BIT
12 bits for transfer
0x4
13_BIT
13 bits for transfer
0x5
14_BIT
14 bits for transfer
0x6
15_BIT
15 bits for transfer
0x7
16_BIT
16 bits for transfer
0x8
CPOL
Clock Polarity
0
1
read-write
CSAAT
Chip Select Active After Transfer
3
1
read-write
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
read-write
DLYBCT
Delay Between Consecutive Transfers
24
8
read-write
DLYBS
Delay Before SPCK
16
8
read-write
NCPHA
Clock Phase
1
1
read-write
SCBR
Serial Clock Baud Rate
8
8
read-write
CSR[0]
Chip Select Register
0x60
32
read-write
n
0x0
0x0
BITS
Bits Per Transfer
4
4
read-write
8_BIT
8 bits for transfer
0x0
9_BIT
9 bits for transfer
0x1
10_BIT
10 bits for transfer
0x2
11_BIT
11 bits for transfer
0x3
12_BIT
12 bits for transfer
0x4
13_BIT
13 bits for transfer
0x5
14_BIT
14 bits for transfer
0x6
15_BIT
15 bits for transfer
0x7
16_BIT
16 bits for transfer
0x8
CPOL
Clock Polarity
0
1
read-write
CSAAT
Chip Select Active After Transfer
3
1
read-write
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
read-write
DLYBCT
Delay Between Consecutive Transfers
24
8
read-write
DLYBS
Delay Before SPCK
16
8
read-write
NCPHA
Clock Phase
1
1
read-write
SCBR
Serial Clock Baud Rate
8
8
read-write
CSR[1]
Chip Select Register
0x94
32
read-write
n
0x0
0x0
BITS
Bits Per Transfer
4
4
read-write
8_BIT
8 bits for transfer
0x0
9_BIT
9 bits for transfer
0x1
10_BIT
10 bits for transfer
0x2
11_BIT
11 bits for transfer
0x3
12_BIT
12 bits for transfer
0x4
13_BIT
13 bits for transfer
0x5
14_BIT
14 bits for transfer
0x6
15_BIT
15 bits for transfer
0x7
16_BIT
16 bits for transfer
0x8
CPOL
Clock Polarity
0
1
read-write
CSAAT
Chip Select Active After Transfer
3
1
read-write
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
read-write
DLYBCT
Delay Between Consecutive Transfers
24
8
read-write
DLYBS
Delay Before SPCK
16
8
read-write
NCPHA
Clock Phase
1
1
read-write
SCBR
Serial Clock Baud Rate
8
8
read-write
CSR[2]
Chip Select Register
0xCC
32
read-write
n
0x0
0x0
BITS
Bits Per Transfer
4
4
read-write
8_BIT
8 bits for transfer
0x0
9_BIT
9 bits for transfer
0x1
10_BIT
10 bits for transfer
0x2
11_BIT
11 bits for transfer
0x3
12_BIT
12 bits for transfer
0x4
13_BIT
13 bits for transfer
0x5
14_BIT
14 bits for transfer
0x6
15_BIT
15 bits for transfer
0x7
16_BIT
16 bits for transfer
0x8
CPOL
Clock Polarity
0
1
read-write
CSAAT
Chip Select Active After Transfer
3
1
read-write
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
read-write
DLYBCT
Delay Between Consecutive Transfers
24
8
read-write
DLYBS
Delay Before SPCK
16
8
read-write
NCPHA
Clock Phase
1
1
read-write
SCBR
Serial Clock Baud Rate
8
8
read-write
CSR[3]
Chip Select Register
0x108
32
read-write
n
0x0
0x0
BITS
Bits Per Transfer
4
4
read-write
8_BIT
8 bits for transfer
0x0
9_BIT
9 bits for transfer
0x1
10_BIT
10 bits for transfer
0x2
11_BIT
11 bits for transfer
0x3
12_BIT
12 bits for transfer
0x4
13_BIT
13 bits for transfer
0x5
14_BIT
14 bits for transfer
0x6
15_BIT
15 bits for transfer
0x7
16_BIT
16 bits for transfer
0x8
CPOL
Clock Polarity
0
1
read-write
CSAAT
Chip Select Active After Transfer
3
1
read-write
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
read-write
DLYBCT
Delay Between Consecutive Transfers
24
8
read-write
DLYBS
Delay Before SPCK
16
8
read-write
NCPHA
Clock Phase
1
1
read-write
SCBR
Serial Clock Baud Rate
8
8
read-write
IDR
Interrupt Disable Register
0x18
32
write-only
n
0x0
0x0
ENDRX
End of Receive Buffer Interrupt Disable
4
1
write-only
ENDTX
End of Transmit Buffer Interrupt Disable
5
1
write-only
MODF
Mode Fault Error Interrupt Disable
2
1
write-only
NSSR
NSS Rising Interrupt Disable
8
1
write-only
OVRES
Overrun Error Interrupt Disable
3
1
write-only
RDRF
Receive Data Register Full Interrupt Disable
0
1
write-only
RXBUFF
Receive Buffer Full Interrupt Disable
6
1
write-only
TDRE
SPI Transmit Data Register Empty Interrupt Disable
1
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Disable
7
1
write-only
TXEMPTY
Transmission Registers Empty Disable
9
1
write-only
UNDES
Underrun Error Interrupt Disable
10
1
write-only
IER
Interrupt Enable Register
0x14
32
write-only
n
0x0
0x0
ENDRX
End of Receive Buffer Interrupt Enable
4
1
write-only
ENDTX
End of Transmit Buffer Interrupt Enable
5
1
write-only
MODF
Mode Fault Error Interrupt Enable
2
1
write-only
NSSR
NSS Rising Interrupt Enable
8
1
write-only
OVRES
Overrun Error Interrupt Enable
3
1
write-only
RDRF
Receive Data Register Full Interrupt Enable
0
1
write-only
RXBUFF
Receive Buffer Full Interrupt Enable
6
1
write-only
TDRE
SPI Transmit Data Register Empty Interrupt Enable
1
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Enable
7
1
write-only
TXEMPTY
Transmission Registers Empty Enable
9
1
write-only
UNDES
Underrun Error Interrupt Enable
10
1
write-only
IMR
Interrupt Mask Register
0x1C
32
read-only
n
0x0
0x0
ENDRX
End of Receive Buffer Interrupt Mask
4
1
read-only
ENDTX
End of Transmit Buffer Interrupt Mask
5
1
read-only
MODF
Mode Fault Error Interrupt Mask
2
1
read-only
NSSR
NSS Rising Interrupt Mask
8
1
read-only
OVRES
Overrun Error Interrupt Mask
3
1
read-only
RDRF
Receive Data Register Full Interrupt Mask
0
1
read-only
RXBUFF
Receive Buffer Full Interrupt Mask
6
1
read-only
TDRE
SPI Transmit Data Register Empty Interrupt Mask
1
1
read-only
TXBUFE
Transmit Buffer Empty Interrupt Mask
7
1
read-only
TXEMPTY
Transmission Registers Empty Mask
9
1
read-only
UNDES
Underrun Error Interrupt Mask
10
1
read-only
MR
Mode Register
0x4
32
read-write
n
0x0
0x0
DLYBCS
Delay Between Chip Selects
24
8
read-write
LLB
Local Loopback Enable
7
1
read-write
MODFDIS
Mode Fault Detection
4
1
read-write
MSTR
Master/Slave Mode
0
1
read-write
PCS
Peripheral Chip Select
16
4
read-write
PCSDEC
Chip Select Decode
2
1
read-write
PS
Peripheral Select
1
1
read-write
WDRBT
Wait Data Read Before Transfer
5
1
read-write
PTCR
Transfer Control Register
0x120
32
write-only
n
0x0
0x0
RXTDIS
Receiver Transfer Disable
1
1
write-only
RXTEN
Receiver Transfer Enable
0
1
write-only
TXTDIS
Transmitter Transfer Disable
9
1
write-only
TXTEN
Transmitter Transfer Enable
8
1
write-only
PTSR
Transfer Status Register
0x124
32
read-only
n
0x0
0x0
RXTEN
Receiver Transfer Enable
0
1
read-only
TXTEN
Transmitter Transfer Enable
8
1
read-only
RCR
Receive Counter Register
0x104
32
read-write
n
0x0
0x0
RXCTR
Receive Counter Register
0
16
read-write
RDR
Receive Data Register
0x8
32
read-only
n
0x0
0x0
PCS
Peripheral Chip Select
16
4
read-only
RD
Receive Data
0
16
read-only
RNCR
Receive Next Counter Register
0x114
32
read-write
n
0x0
0x0
RXNCTR
Receive Next Counter
0
16
read-write
RNPR
Receive Next Pointer Register
0x110
32
read-write
n
0x0
0x0
RXNPTR
Receive Next Pointer
0
32
read-write
RPR
Receive Pointer Register
0x100
32
read-write
n
0x0
0x0
RXPTR
Receive Pointer Register
0
32
read-write
SR
Status Register
0x10
32
read-only
n
0x0
0x0
ENDRX
End of RX Buffer (automatically set / cleared)
4
1
read-only
ENDTX
End of TX Buffer (automatically set / cleared)
5
1
read-only
MODF
Mode Fault Error (cleared on read)
2
1
read-only
NSSR
NSS Rising (cleared on read)
8
1
read-only
OVRES
Overrun Error Status (cleared on read)
3
1
read-only
RDRF
Receive Data Register Full (automatically set / cleared)
0
1
read-only
RXBUFF
RX Buffer Full (automatically set / cleared)
6
1
read-only
SPIENS
SPI Enable Status
16
1
read-only
TDRE
Transmit Data Register Empty (automatically set / cleared)
1
1
read-only
TXBUFE
TX Buffer Empty (automatically set / cleared)
7
1
read-only
TXEMPTY
Transmission Registers Empty (automatically set / cleared)
9
1
read-only
UNDES
Underrun Error Status (Slave mode only) (cleared on read)
10
1
read-only
TCR
Transmit Counter Register
0x10C
32
read-write
n
0x0
0x0
TXCTR
Transmit Counter Register
0
16
read-write
TDR
Transmit Data Register
0xC
32
write-only
n
0x0
0x0
LASTXFER
Last Transfer
24
1
write-only
PCS
Peripheral Chip Select
16
4
write-only
TD
Transmit Data
0
16
write-only
TNCR
Transmit Next Counter Register
0x11C
32
read-write
n
0x0
0x0
TXNCTR
Transmit Counter Next
0
16
read-write
TNPR
Transmit Next Pointer Register
0x118
32
read-write
n
0x0
0x0
TXNPTR
Transmit Next Pointer
0
32
read-write
TPR
Transmit Pointer Register
0x108
32
read-write
n
0x0
0x0
TXPTR
Transmit Counter Register
0
32
read-write
WPMR
Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protection Enable
0
1
read-write
WPKEY
Write Protection Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
0x535049
WPSR
Write Protection Status Register
0xE8
32
read-only
n
0x0
0x0
WPVS
Write Protection Violation Status
0
1
read-only
WPVSRC
Write Protection Violation Source
8
8
read-only
SPI1
Serial Peripheral Interface 1
SPI
0x0
0x0
0x50
registers
n
SPI1
40
CR
Control Register
0x0
32
write-only
n
0x0
0x0
LASTXFER
Last Transfer
24
1
write-only
SPIDIS
SPI Disable
1
1
write-only
SPIEN
SPI Enable
0
1
write-only
SWRST
SPI Software Reset
7
1
write-only
CSR0
Chip Select Register
0x30
32
read-write
n
BITS
Bits Per Transfer
4
4
read-write
8_BIT
8 bits for transfer
0x0
9_BIT
9 bits for transfer
0x1
10_BIT
10 bits for transfer
0x2
11_BIT
11 bits for transfer
0x3
12_BIT
12 bits for transfer
0x4
13_BIT
13 bits for transfer
0x5
14_BIT
14 bits for transfer
0x6
15_BIT
15 bits for transfer
0x7
16_BIT
16 bits for transfer
0x8
CPOL
Clock Polarity
0
1
read-write
CSAAT
Chip Select Active After Transfer
3
1
read-write
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
read-write
DLYBCT
Delay Between Consecutive Transfers
24
8
read-write
DLYBS
Delay Before SPCK
16
8
read-write
NCPHA
Clock Phase
1
1
read-write
SCBR
Serial Clock Baud Rate
8
8
read-write
CSR1
Chip Select Register
0x34
32
read-write
n
BITS
Bits Per Transfer
4
4
read-write
8_BIT
8 bits for transfer
0x0
9_BIT
9 bits for transfer
0x1
10_BIT
10 bits for transfer
0x2
11_BIT
11 bits for transfer
0x3
12_BIT
12 bits for transfer
0x4
13_BIT
13 bits for transfer
0x5
14_BIT
14 bits for transfer
0x6
15_BIT
15 bits for transfer
0x7
16_BIT
16 bits for transfer
0x8
CPOL
Clock Polarity
0
1
read-write
CSAAT
Chip Select Active After Transfer
3
1
read-write
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
read-write
DLYBCT
Delay Between Consecutive Transfers
24
8
read-write
DLYBS
Delay Before SPCK
16
8
read-write
NCPHA
Clock Phase
1
1
read-write
SCBR
Serial Clock Baud Rate
8
8
read-write
CSR2
Chip Select Register
0x38
32
read-write
n
BITS
Bits Per Transfer
4
4
read-write
8_BIT
8 bits for transfer
0x0
9_BIT
9 bits for transfer
0x1
10_BIT
10 bits for transfer
0x2
11_BIT
11 bits for transfer
0x3
12_BIT
12 bits for transfer
0x4
13_BIT
13 bits for transfer
0x5
14_BIT
14 bits for transfer
0x6
15_BIT
15 bits for transfer
0x7
16_BIT
16 bits for transfer
0x8
CPOL
Clock Polarity
0
1
read-write
CSAAT
Chip Select Active After Transfer
3
1
read-write
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
read-write
DLYBCT
Delay Between Consecutive Transfers
24
8
read-write
DLYBS
Delay Before SPCK
16
8
read-write
NCPHA
Clock Phase
1
1
read-write
SCBR
Serial Clock Baud Rate
8
8
read-write
CSR3
Chip Select Register
0x3C
32
read-write
n
BITS
Bits Per Transfer
4
4
read-write
8_BIT
8 bits for transfer
0x0
9_BIT
9 bits for transfer
0x1
10_BIT
10 bits for transfer
0x2
11_BIT
11 bits for transfer
0x3
12_BIT
12 bits for transfer
0x4
13_BIT
13 bits for transfer
0x5
14_BIT
14 bits for transfer
0x6
15_BIT
15 bits for transfer
0x7
16_BIT
16 bits for transfer
0x8
CPOL
Clock Polarity
0
1
read-write
CSAAT
Chip Select Active After Transfer
3
1
read-write
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
read-write
DLYBCT
Delay Between Consecutive Transfers
24
8
read-write
DLYBS
Delay Before SPCK
16
8
read-write
NCPHA
Clock Phase
1
1
read-write
SCBR
Serial Clock Baud Rate
8
8
read-write
CSR[0]
Chip Select Register
0x60
32
read-write
n
0x0
0x0
BITS
Bits Per Transfer
4
4
read-write
8_BIT
8 bits for transfer
0x0
9_BIT
9 bits for transfer
0x1
10_BIT
10 bits for transfer
0x2
11_BIT
11 bits for transfer
0x3
12_BIT
12 bits for transfer
0x4
13_BIT
13 bits for transfer
0x5
14_BIT
14 bits for transfer
0x6
15_BIT
15 bits for transfer
0x7
16_BIT
16 bits for transfer
0x8
CPOL
Clock Polarity
0
1
read-write
CSAAT
Chip Select Active After Transfer
3
1
read-write
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
read-write
DLYBCT
Delay Between Consecutive Transfers
24
8
read-write
DLYBS
Delay Before SPCK
16
8
read-write
NCPHA
Clock Phase
1
1
read-write
SCBR
Serial Clock Baud Rate
8
8
read-write
CSR[1]
Chip Select Register
0x94
32
read-write
n
0x0
0x0
BITS
Bits Per Transfer
4
4
read-write
8_BIT
8 bits for transfer
0x0
9_BIT
9 bits for transfer
0x1
10_BIT
10 bits for transfer
0x2
11_BIT
11 bits for transfer
0x3
12_BIT
12 bits for transfer
0x4
13_BIT
13 bits for transfer
0x5
14_BIT
14 bits for transfer
0x6
15_BIT
15 bits for transfer
0x7
16_BIT
16 bits for transfer
0x8
CPOL
Clock Polarity
0
1
read-write
CSAAT
Chip Select Active After Transfer
3
1
read-write
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
read-write
DLYBCT
Delay Between Consecutive Transfers
24
8
read-write
DLYBS
Delay Before SPCK
16
8
read-write
NCPHA
Clock Phase
1
1
read-write
SCBR
Serial Clock Baud Rate
8
8
read-write
CSR[2]
Chip Select Register
0xCC
32
read-write
n
0x0
0x0
BITS
Bits Per Transfer
4
4
read-write
8_BIT
8 bits for transfer
0x0
9_BIT
9 bits for transfer
0x1
10_BIT
10 bits for transfer
0x2
11_BIT
11 bits for transfer
0x3
12_BIT
12 bits for transfer
0x4
13_BIT
13 bits for transfer
0x5
14_BIT
14 bits for transfer
0x6
15_BIT
15 bits for transfer
0x7
16_BIT
16 bits for transfer
0x8
CPOL
Clock Polarity
0
1
read-write
CSAAT
Chip Select Active After Transfer
3
1
read-write
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
read-write
DLYBCT
Delay Between Consecutive Transfers
24
8
read-write
DLYBS
Delay Before SPCK
16
8
read-write
NCPHA
Clock Phase
1
1
read-write
SCBR
Serial Clock Baud Rate
8
8
read-write
CSR[3]
Chip Select Register
0x108
32
read-write
n
0x0
0x0
BITS
Bits Per Transfer
4
4
read-write
8_BIT
8 bits for transfer
0x0
9_BIT
9 bits for transfer
0x1
10_BIT
10 bits for transfer
0x2
11_BIT
11 bits for transfer
0x3
12_BIT
12 bits for transfer
0x4
13_BIT
13 bits for transfer
0x5
14_BIT
14 bits for transfer
0x6
15_BIT
15 bits for transfer
0x7
16_BIT
16 bits for transfer
0x8
CPOL
Clock Polarity
0
1
read-write
CSAAT
Chip Select Active After Transfer
3
1
read-write
CSNAAT
Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
2
1
read-write
DLYBCT
Delay Between Consecutive Transfers
24
8
read-write
DLYBS
Delay Before SPCK
16
8
read-write
NCPHA
Clock Phase
1
1
read-write
SCBR
Serial Clock Baud Rate
8
8
read-write
IDR
Interrupt Disable Register
0x18
32
write-only
n
0x0
0x0
ENDRX
End of Receive Buffer Interrupt Disable
4
1
write-only
ENDTX
End of Transmit Buffer Interrupt Disable
5
1
write-only
MODF
Mode Fault Error Interrupt Disable
2
1
write-only
NSSR
NSS Rising Interrupt Disable
8
1
write-only
OVRES
Overrun Error Interrupt Disable
3
1
write-only
RDRF
Receive Data Register Full Interrupt Disable
0
1
write-only
RXBUFF
Receive Buffer Full Interrupt Disable
6
1
write-only
TDRE
SPI Transmit Data Register Empty Interrupt Disable
1
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Disable
7
1
write-only
TXEMPTY
Transmission Registers Empty Disable
9
1
write-only
UNDES
Underrun Error Interrupt Disable
10
1
write-only
IER
Interrupt Enable Register
0x14
32
write-only
n
0x0
0x0
ENDRX
End of Receive Buffer Interrupt Enable
4
1
write-only
ENDTX
End of Transmit Buffer Interrupt Enable
5
1
write-only
MODF
Mode Fault Error Interrupt Enable
2
1
write-only
NSSR
NSS Rising Interrupt Enable
8
1
write-only
OVRES
Overrun Error Interrupt Enable
3
1
write-only
RDRF
Receive Data Register Full Interrupt Enable
0
1
write-only
RXBUFF
Receive Buffer Full Interrupt Enable
6
1
write-only
TDRE
SPI Transmit Data Register Empty Interrupt Enable
1
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Enable
7
1
write-only
TXEMPTY
Transmission Registers Empty Enable
9
1
write-only
UNDES
Underrun Error Interrupt Enable
10
1
write-only
IMR
Interrupt Mask Register
0x1C
32
read-only
n
0x0
0x0
ENDRX
End of Receive Buffer Interrupt Mask
4
1
read-only
ENDTX
End of Transmit Buffer Interrupt Mask
5
1
read-only
MODF
Mode Fault Error Interrupt Mask
2
1
read-only
NSSR
NSS Rising Interrupt Mask
8
1
read-only
OVRES
Overrun Error Interrupt Mask
3
1
read-only
RDRF
Receive Data Register Full Interrupt Mask
0
1
read-only
RXBUFF
Receive Buffer Full Interrupt Mask
6
1
read-only
TDRE
SPI Transmit Data Register Empty Interrupt Mask
1
1
read-only
TXBUFE
Transmit Buffer Empty Interrupt Mask
7
1
read-only
TXEMPTY
Transmission Registers Empty Mask
9
1
read-only
UNDES
Underrun Error Interrupt Mask
10
1
read-only
MR
Mode Register
0x4
32
read-write
n
0x0
0x0
DLYBCS
Delay Between Chip Selects
24
8
read-write
LLB
Local Loopback Enable
7
1
read-write
MODFDIS
Mode Fault Detection
4
1
read-write
MSTR
Master/Slave Mode
0
1
read-write
PCS
Peripheral Chip Select
16
4
read-write
PCSDEC
Chip Select Decode
2
1
read-write
PS
Peripheral Select
1
1
read-write
WDRBT
Wait Data Read Before Transfer
5
1
read-write
PTCR
Transfer Control Register
0x120
32
write-only
n
0x0
0x0
RXTDIS
Receiver Transfer Disable
1
1
write-only
RXTEN
Receiver Transfer Enable
0
1
write-only
TXTDIS
Transmitter Transfer Disable
9
1
write-only
TXTEN
Transmitter Transfer Enable
8
1
write-only
PTSR
Transfer Status Register
0x124
32
read-only
n
0x0
0x0
RXTEN
Receiver Transfer Enable
0
1
read-only
TXTEN
Transmitter Transfer Enable
8
1
read-only
RCR
Receive Counter Register
0x104
32
read-write
n
0x0
0x0
RXCTR
Receive Counter Register
0
16
read-write
RDR
Receive Data Register
0x8
32
read-only
n
0x0
0x0
PCS
Peripheral Chip Select
16
4
read-only
RD
Receive Data
0
16
read-only
RNCR
Receive Next Counter Register
0x114
32
read-write
n
0x0
0x0
RXNCTR
Receive Next Counter
0
16
read-write
RNPR
Receive Next Pointer Register
0x110
32
read-write
n
0x0
0x0
RXNPTR
Receive Next Pointer
0
32
read-write
RPR
Receive Pointer Register
0x100
32
read-write
n
0x0
0x0
RXPTR
Receive Pointer Register
0
32
read-write
SR
Status Register
0x10
32
read-only
n
0x0
0x0
ENDRX
End of RX Buffer (automatically set / cleared)
4
1
read-only
ENDTX
End of TX Buffer (automatically set / cleared)
5
1
read-only
MODF
Mode Fault Error (cleared on read)
2
1
read-only
NSSR
NSS Rising (cleared on read)
8
1
read-only
OVRES
Overrun Error Status (cleared on read)
3
1
read-only
RDRF
Receive Data Register Full (automatically set / cleared)
0
1
read-only
RXBUFF
RX Buffer Full (automatically set / cleared)
6
1
read-only
SPIENS
SPI Enable Status
16
1
read-only
TDRE
Transmit Data Register Empty (automatically set / cleared)
1
1
read-only
TXBUFE
TX Buffer Empty (automatically set / cleared)
7
1
read-only
TXEMPTY
Transmission Registers Empty (automatically set / cleared)
9
1
read-only
UNDES
Underrun Error Status (Slave mode only) (cleared on read)
10
1
read-only
TCR
Transmit Counter Register
0x10C
32
read-write
n
0x0
0x0
TXCTR
Transmit Counter Register
0
16
read-write
TDR
Transmit Data Register
0xC
32
write-only
n
0x0
0x0
LASTXFER
Last Transfer
24
1
write-only
PCS
Peripheral Chip Select
16
4
write-only
TD
Transmit Data
0
16
write-only
TNCR
Transmit Next Counter Register
0x11C
32
read-write
n
0x0
0x0
TXNCTR
Transmit Counter Next
0
16
read-write
TNPR
Transmit Next Pointer Register
0x118
32
read-write
n
0x0
0x0
TXNPTR
Transmit Next Pointer
0
32
read-write
TPR
Transmit Pointer Register
0x108
32
read-write
n
0x0
0x0
TXPTR
Transmit Counter Register
0
32
read-write
WPMR
Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protection Enable
0
1
read-write
WPKEY
Write Protection Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
0x535049
WPSR
Write Protection Status Register
0xE8
32
read-only
n
0x0
0x0
WPVS
Write Protection Violation Status
0
1
read-only
WPVSRC
Write Protection Violation Source
8
8
read-only
SUPC
Supply Controller
SYSC
0x0
0x0
0x200
registers
n
CR
Supply Controller Control Register
0x0
32
write-only
n
0x0
0x0
KEY
Password
24
8
write-only
PASSWD
Writing any other value in this field aborts the write operation.
0xA5
VROFF
Voltage Regulator Off
2
1
write-only
NO_EFFECT
No effect.
0
STOP_VREG
If KEY is correct, asserts the system reset signal and stops the voltage regulator.
1
XTALSEL
Crystal Oscillator Select
3
1
write-only
NO_EFFECT
No effect.
0
CRYSTAL_SEL
If KEY is correct, switches the slow clock on the crystal oscillator output.
1
MR
Supply Controller Mode Register
0x8
32
read-write
n
0x0
0x0
BODDIS
Brownout Detector Disable
13
1
read-write
ENABLE
The core brownout detector is enabled.
0
DISABLE
The core brownout detector is disabled.
1
BODRSTEN
Brownout Detector Reset Enable
12
1
read-write
NOT_ENABLE
The system reset signal is not affected when a brownout detection occurs.
0
ENABLE
The system reset signal is asserted when a brownout detection occurs.
1
BUPPOREN
Backup Area Power-On Reset Enable
15
1
read-write
BUPPOR_DISABLE
Disables the backup POR.
0
BUPPOR_ENABLE
Enables the backup POR.
1
KEY
Password Key
24
8
read-write
PASSWD
Writing any other value in this field aborts the write operation.
0xA5
LCDMODE
LCD Controller Mode of Operation
4
2
read-write
LCDOFF
The internal supply source and the external supply source are both deselected (OFF mode).
0x0
LCDON_EXTVR
The external supply source for LCD (VDDLCD) is selected (the LCD voltage regulator is in Hi-Z mode).
0x2
LCDON_INVR
The internal supply source for LCD (the LCD Voltage Regulator) is selected (Active mode).
0x3
LCDVROUT
LCD Voltage Regulator Output
0
4
read-write
ONREG
Voltage Regulator enable
14
1
read-write
ONREG_UNUSED
Internal voltage regulator is not used (external power supply is used).
0
ONREG_USED
Internal voltage regulator is used.
1
OSCBYPASS
Oscillator Bypass
20
1
read-write
NO_EFFECT
No effect. Clock selection depends on XTALSEL value.
0
BYPASS
The 32 kHz crystal oscillator is bypassed if XTALSEL = 1. OSCBYPASS must be set before setting XTALSEL.
1
SMMR
Supply Controller Supply Monitor Mode Register
0x4
32
read-write
n
0x0
0x0
SMIEN
Supply Monitor Interrupt Enable
13
1
read-write
NOT_ENABLE
The SUPC interrupt signal is not affected when a supply monitor detection occurs.
0
ENABLE
The SUPC interrupt signal is asserted when a supply monitor detection occurs.
1
SMRSTEN
Supply Monitor Reset Enable
12
1
read-write
NOT_ENABLE
The system reset signal is not affected when a supply monitor detection occurs.
0
ENABLE
The system reset signal is asserted when a supply monitor detection occurs.
1
SMSMPL
Supply Monitor Sampling Period
8
3
read-write
SMD
Supply Monitor disabled
0x0
CSM
Continuous Supply Monitor
0x1
32SLCK
Supply Monitor enabled one SLCK period every 32 SLCK periods
0x2
256SLCK
Supply Monitor enabled one SLCK period every 256 SLCK periods
0x3
2048SLCK
Supply Monitor enabled one SLCK period every 2,048 SLCK periods
0x4
SMTH
Supply Monitor Threshold
0
4
read-write
SR
Supply Controller Status Register
0x14
32
read-only
n
0x0
0x0
BODRSTS
Brownout Detector Reset Status (cleared on read)
3
1
read-only
NO
No core brownout rising edge event has been detected since the last read of SUPC_SR.
0
PRESENT
At least one brownout output rising edge event has been detected since the last read of SUPC_SR.
1
BUPPORS
Backup Area Power-On Reset Status
15
1
read-only
BUPPOR_DISABLED
Backup POR is disabled.
0
BUPPOR_ENABLED
Backup POR is enabled.
1
FWUPIS
FWUP Input Status
12
1
read-only
LOW
FWUP input is tied low.
0
HIGH
FWUP input is tied high.
1
FWUPS
FWUP Wake-up Status (cleared on read)
0
1
read-only
NO
No wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR.
0
PRESENT
At least one wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR.
1
LCDS
LCD Status
8
1
read-only
DISABLED
LCD controller is disabled.
0
ENABLED
LCD controller is enabled.
1
LPDBCS0
Low Power Debouncer Wake-up Status on WKUP0/TMP0 (cleared on read)
13
1
read-only
NO
No tamper detection or wake-up due to the assertion of the WKUP0/TMP0 pin has occurred since the last read of SUPC_SR.
0
PRESENT
At least one tamper detection and wake-up (if enabled by WKUPEN0) due to the assertion of the WKUP0/TMP0 pin has occurred since the last read of SUPC_SR. The SUPC interrupt line is asserted while LPDBCS0 is 1.
1
LPDBCS1
Low Power Debouncer Wake-up Status on WKUP10/TMP1 (cleared on read)
14
1
read-only
NO
No tamper detection or wake-up due to the assertion of the WKUP10 pin has occurred since the last read of SUPC_SR.
0
PRESENT
At least one tamper detection and wake-up (if enabled by WKUPEN10) due to the assertion of the WKUP10/TMP1 pin has occurred since the last read of SUPC_SR. The SUPC interrupt line is asserted while LPDBCS1 is 1.
1
OSCSEL
32 kHz Oscillator Selection Status
7
1
read-only
RC
The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator.
0
CRYST
The slow clock, SLCK, is generated by the 32 kHz crystal oscillator.
1
SMOS
Supply Monitor Output Status
6
1
read-only
HIGH
The supply monitor detected VDDIO higher than its threshold at its last measurement.
0
LOW
The supply monitor detected VDDIO lower than its threshold at its last measurement.
1
SMRSTS
Supply Monitor Reset Status (cleared on read)
4
1
read-only
NO
No supply monitor detection has generated a system reset since the last read of SUPC_SR.
0
PRESENT
At least one supply monitor detection has generated a system reset since the last read of SUPC_SR.
1
SMS
Supply Monitor Status (cleared on read)
5
1
read-only
NO
No supply monitor detection since the last read of SUPC_SR.
0
PRESENT
At least one supply monitor detection since the last read of SUPC_SR.
1
SMWS
Supply Monitor Detection Wake-up Status (cleared on read)
2
1
read-only
NO
No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.
0
PRESENT
At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.
1
WKUPIS0
WKUPx Input Status (cleared on read)
16
1
read-only
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS1
WKUPx Input Status (cleared on read)
17
1
read-only
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS10
WKUPx Input Status (cleared on read)
26
1
read-only
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS11
WKUPx Input Status (cleared on read)
27
1
read-only
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS12
WKUPx Input Status (cleared on read)
28
1
read-only
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS2
WKUPx Input Status (cleared on read)
18
1
read-only
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS3
WKUPx Input Status (cleared on read)
19
1
read-only
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS4
WKUPx Input Status (cleared on read)
20
1
read-only
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS5
WKUPx Input Status (cleared on read)
21
1
read-only
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS6
WKUPx Input Status (cleared on read)
22
1
read-only
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS7
WKUPx Input Status (cleared on read)
23
1
read-only
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS8
WKUPx Input Status (cleared on read)
24
1
read-only
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPIS9
WKUPx Input Status (cleared on read)
25
1
read-only
DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
0
EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR.
1
WKUPS
WKUP Wake-up Status (cleared on read)
1
1
read-only
NO
No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
0
PRESENT
At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
1
WUIR
Supply Controller Wake-up Inputs Register
0x10
32
read-write
n
0x0
0x0
WKUPEN0
WKUPx Input Enable
0
1
read-write
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input forces a system wake-up.
1
WKUPEN1
WKUPx Input Enable
1
1
read-write
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input forces a system wake-up.
1
WKUPEN10
WKUPx Input Enable
10
1
read-write
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input forces a system wake-up.
1
WKUPEN11
WKUPx Input Enable
11
1
read-write
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input forces a system wake-up.
1
WKUPEN12
WKUPx Input Enable
12
1
read-write
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input forces a system wake-up.
1
WKUPEN13
WKUPx Input Enable
13
1
read-write
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input forces a system wake-up.
1
WKUPEN14
WKUPx Input Enable
14
1
read-write
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input forces a system wake-up.
1
WKUPEN15
WKUPx Input Enable
15
1
read-write
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input forces a system wake-up.
1
WKUPEN2
WKUPx Input Enable
2
1
read-write
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input forces a system wake-up.
1
WKUPEN3
WKUPx Input Enable
3
1
read-write
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input forces a system wake-up.
1
WKUPEN4
WKUPx Input Enable
4
1
read-write
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input forces a system wake-up.
1
WKUPEN5
WKUPx Input Enable
5
1
read-write
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input forces a system wake-up.
1
WKUPEN6
WKUPx Input Enable
6
1
read-write
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input forces a system wake-up.
1
WKUPEN7
WKUPx Input Enable
7
1
read-write
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input forces a system wake-up.
1
WKUPEN8
WKUPx Input Enable
8
1
read-write
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input forces a system wake-up.
1
WKUPEN9
WKUPx Input Enable
9
1
read-write
DISABLE
The corresponding wake-up input has no wake-up effect.
0
ENABLE
The corresponding wake-up input forces a system wake-up.
1
WKUPT0
WKUPx Input Type
16
1
read-write
LOW
A low level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
0
HIGH
A high level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
1
WKUPT1
WKUPx Input Type
17
1
read-write
LOW
A low level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
0
HIGH
A high level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
1
WKUPT10
WKUPx Input Type
26
1
read-write
LOW
A low level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
0
HIGH
A high level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
1
WKUPT11
WKUPx Input Type
27
1
read-write
LOW
A low level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
0
HIGH
A high level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
1
WKUPT12
WKUPx Input Type
28
1
read-write
LOW
A low level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
0
HIGH
A high level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
1
WKUPT2
WKUPx Input Type
18
1
read-write
LOW
A low level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
0
HIGH
A high level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
1
WKUPT3
WKUPx Input Type
19
1
read-write
LOW
A low level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
0
HIGH
A high level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
1
WKUPT4
WKUPx Input Type
20
1
read-write
LOW
A low level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
0
HIGH
A high level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
1
WKUPT5
WKUPx Input Type
21
1
read-write
LOW
A low level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
0
HIGH
A high level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
1
WKUPT6
WKUPx Input Type
22
1
read-write
LOW
A low level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
0
HIGH
A high level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
1
WKUPT7
WKUPx Input Type
23
1
read-write
LOW
A low level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
0
HIGH
A high level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
1
WKUPT8
WKUPx Input Type
24
1
read-write
LOW
A low level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
0
HIGH
A high level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
1
WKUPT9
WKUPx Input Type
25
1
read-write
LOW
A low level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
0
HIGH
A high level for a period defined by WKUPDBC in SUPC_WUMR on the corresponding wake-up input forces a system wake-up.
1
WUMR
Supply Controller Wake-up Mode Register
0xC
32
read-write
n
0x0
0x0
DISTMPCLR1
Disable GPBR Clear Command from WKUP10/TMP1 pin
24
1
read-write
ENABLE
The WKUP10/TMP1 input pin can clear the GPBR (if LPDBCCLR is enabled) when tamper is detected.
0
DISABLE
The WKUP10/TMP1 input pin has no effect on the GPBR value (no clear on tamper detection).
1
DISTSTMP1
Disable Timestamp from WKUP10/TMP1 Pin
28
1
read-write
ENABLE
A tamper detection on WKUP10/TMP1 pin generates a timestamp.
0
DISABLE
A tamper detection on WKUP10/TMP1 does NOT generate a report in timestamp register.
1
FWUPDBC
Force Wake-up Debouncer Period
8
3
read-write
IMMEDIATE
Immediate, no debouncing, detected active at least on one Slow Clock edge.
0x0
3_SCLK
FWUP shall be low for at least 3 SLCK periods
0x1
32_SCLK
FWUP shall be low for at least 32 SLCK periods
0x2
512_SCLK
FWUP shall be low for at least 512 SLCK periods
0x3
4096_SCLK
FWUP shall be low for at least 4,096 SLCK periods
0x4
32768_SCLK
FWUP shall be low for at least 32,768 SLCK periods
0x5
FWUPEN
Force Wake-up Enable
0
1
read-write
NOT_ENABLE
The force wake-up pin has no wake-up effect.
0
ENABLE
The force wake-up pin low forces a system wake-up.
1
LPDBC
Low Power Debouncer Period
16
3
read-write
DISABLE
Disable the low-power debouncers.
0x0
2_RTCOUT0
WKUP0/10TMP0/1 in active state for at least 2 RTCOUT0 periods
0x1
3_RTCOUT0
WKUP0/10TMP0/1 in active state for at least 3 RTCOUT0 periods
0x2
4_RTCOUT0
WKUP0/10TMP0/1 in active state for at least 4 RTCOUT0 periods
0x3
5_RTCOUT0
WKUP0/10TMP0/1 in active state for at least 5 RTCOUT0 periods
0x4
6_RTCOUT0
WKUP0/10TMP0/1 in active state for at least 6 RTCOUT0 periods
0x5
7_RTCOUT0
WKUP0/10TMP0/1 in active state for at least 7 RTCOUT0 periods
0x6
8_RTCOUT0
WKUP0/10TMP0/1 in active state for at least 8 RTCOUT0 periods
0x7
LPDBCCLR
Low-Power Debouncer Clear
7
1
read-write
NOT_ENABLE
A low-power debounce event does not create an immediate clear on the first half of GPBR registers.
0
ENABLE
A low-power debounce event on WKUP0/TMP0 or WKUP10TMP1(if DISTMPCLR1 is cleared) generates an immediate clear on the first half of GPBR registers.
1
LPDBCEN0
Low-Power Debouncer Enable WKUP0/TMP0
5
1
read-write
NOT_ENABLE
The WKUP0/TMP0 input pin is not connected to the low-power debouncer.
0
ENABLE
The WKUP0/TMP0 input pin is connected to the low-power debouncer and can force a system wake-up.
1
LPDBCEN1
Low-Power Debouncer Enable WKUP10/TMP1
6
1
read-write
NOT_ENABLE
The WKUP10/TMP1 input pin is not connected to the low-power debouncer.
0
ENABLE
The WKUP10/TMP1 input pin is connected to the low-power debouncer and can force a system wake-up.
1
RTCEN
Real-time Clock Wake-up Enable
3
1
read-write
NOT_ENABLE
The RTC alarm signal has no wake-up effect.
0
ENABLE
The RTC alarm signal forces a system wake-up.
1
RTTEN
Real-time Timer Wake-up Enable
2
1
read-write
NOT_ENABLE
The RTT alarm signal has no wake-up effect.
0
ENABLE
The RTT alarm signal forces a system wake-up.
1
SMEN
Supply Monitor Wake-up Enable
1
1
read-write
NOT_ENABLE
The supply monitor detection has no wake-up effect.
0
ENABLE
The supply monitor detection forces a system wake-up.
1
WKUPDBC
Wake-up Inputs Debouncer Period
12
3
read-write
IMMEDIATE
Immediate, no debouncing, detected active at least on one Slow Clock edge.
0x0
3_SCLK
WKUPx shall be in its active state for at least 3 SLCK periods
0x1
32_SCLK
WKUPx shall be in its active state for at least 32 SLCK periods
0x2
512_SCLK
WKUPx shall be in its active state for at least 512 SLCK periods
0x3
4096_SCLK
WKUPx shall be in its active state for at least 4,096 SLCK periods
0x4
32768_SCLK
WKUPx shall be in its active state for at least 32,768 SLCK periods
0x5
TC0
Timer Counter 0
TC
0x0
0x0
0x50
registers
n
TC0
23
TC1
24
TC2
25
BCR
Block Control Register
0xC0
32
write-only
n
0x0
0x0
SYNC
Synchro Command
0
1
write-only
BMR
Block Mode Register
0xC4
32
read-write
n
0x0
0x0
AUTOC
Auto-Correction of missing pulses
18
1
read-write
DISABLED
The detection and auto-correction function is disabled.
0
ENABLED
The detection and auto-correction function is enabled.
1
EDGPHA
Edge on PHA Count Mode
12
1
read-write
IDXPHB
Index Pin is PHB Pin
17
1
read-write
INVA
Inverted PHA
13
1
read-write
INVB
Inverted PHB
14
1
read-write
INVIDX
Inverted Index
15
1
read-write
MAXCMP
Maximum Consecutive Missing Pulses
26
4
read-write
MAXFILT
Maximum Filter
20
6
read-write
POSEN
Position Enabled
9
1
read-write
QDEN
Quadrature Decoder Enabled
8
1
read-write
QDTRANS
Quadrature Decoding Transparent
11
1
read-write
SPEEDEN
Speed Enabled
10
1
read-write
SWAP
Swap PHA and PHB
16
1
read-write
TC0XC0S
External Clock Signal 0 Selection
0
2
read-write
TCLK0
Signal connected to XC0: TCLK0
0x0
TIOA1
Signal connected to XC0: TIOA1
0x2
TIOA2
Signal connected to XC0: TIOA2
0x3
TC1XC1S
External Clock Signal 1 Selection
2
2
read-write
TCLK1
Signal connected to XC1: TCLK1
0x0
TIOA0
Signal connected to XC1: TIOA0
0x2
TIOA2
Signal connected to XC1: TIOA2
0x3
TC2XC2S
External Clock Signal 2 Selection
4
2
read-write
TCLK2
Signal connected to XC2: TCLK2
0x0
TIOA0
Signal connected to XC2: TIOA0
0x2
TIOA1
Signal connected to XC2: TIOA1
0x3
CCR0
Channel Control Register (channel = 0)
0x0
32
write-only
n
0x0
0x0
CLKDIS
Counter Clock Disable Command
1
1
write-only
CLKEN
Counter Clock Enable Command
0
1
write-only
SWTRG
Software Trigger Command
2
1
write-only
CCR1
Channel Control Register (channel = 1)
0x40
32
write-only
n
0x0
0x0
CLKDIS
Counter Clock Disable Command
1
1
write-only
CLKEN
Counter Clock Enable Command
0
1
write-only
SWTRG
Software Trigger Command
2
1
write-only
CCR2
Channel Control Register (channel = 2)
0x80
32
write-only
n
0x0
0x0
CLKDIS
Counter Clock Disable Command
1
1
write-only
CLKEN
Counter Clock Enable Command
0
1
write-only
SWTRG
Software Trigger Command
2
1
write-only
CMR0
Channel Mode Register (channel = 0)
0x4
32
read-write
n
0x0
0x0
ABETRG
TIOA or TIOB External Trigger Selection
10
1
read-write
BURST
Burst Signal Selection
4
2
read-write
NONE
The clock is not gated by an external signal.
0x0
XC0
XC0 is ANDed with the selected clock.
0x1
XC1
XC1 is ANDed with the selected clock.
0x2
XC2
XC2 is ANDed with the selected clock.
0x3
CLKI
Clock Invert
3
1
read-write
CPCTRG
RC Compare Trigger Enable
14
1
read-write
ETRGEDG
External Trigger Edge Selection
8
2
read-write
NONE
The clock is not gated by an external signal.
0x0
RISING
Rising edge
0x1
FALLING
Falling edge
0x2
EDGE
Each edge
0x3
LDBDIS
Counter Clock Disable with RB Loading
7
1
read-write
LDBSTOP
Counter Clock Stopped with RB Loading
6
1
read-write
LDRA
RA Loading Edge Selection
16
2
read-write
NONE
None
0x0
RISING
Rising edge of TIOA
0x1
FALLING
Falling edge of TIOA
0x2
EDGE
Each edge of TIOA
0x3
LDRB
RB Loading Edge Selection
18
2
read-write
NONE
None
0x0
RISING
Rising edge of TIOA
0x1
FALLING
Falling edge of TIOA
0x2
EDGE
Each edge of TIOA
0x3
TCCLKS
Clock Selection
0
3
read-write
TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x0
TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x1
TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x2
TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x3
TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x4
XC0
Clock selected: XC0
0x5
XC1
Clock selected: XC1
0x6
XC2
Clock selected: XC2
0x7
WAVE
Waveform Mode
15
1
read-write
CMR0_WAVE_EQ_1
Channel Mode Register (channel = 0)
WAVE_EQ_1
0x4
32
read-write
n
0x0
0x0
ACPA
RA Compare Effect on TIOA
16
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
ACPC
RC Compare Effect on TIOA
18
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
AEEVT
External Event Effect on TIOA
20
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
ASWTRG
Software Trigger Effect on TIOA
22
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BCPB
RB Compare Effect on TIOB
24
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BCPC
RC Compare Effect on TIOB
26
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BEEVT
External Event Effect on TIOB
28
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BSWTRG
Software Trigger Effect on TIOB
30
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BURST
Burst Signal Selection
4
2
read-write
NONE
The clock is not gated by an external signal.
0x0
XC0
XC0 is ANDed with the selected clock.
0x1
XC1
XC1 is ANDed with the selected clock.
0x2
XC2
XC2 is ANDed with the selected clock.
0x3
CLKI
Clock Invert
3
1
read-write
CPCDIS
Counter Clock Disable with RC Compare
7
1
read-write
CPCSTOP
Counter Clock Stopped with RC Compare
6
1
read-write
EEVT
External Event Selection
10
2
read-write
TIOB
TIOB
0x0
XC0
XC0
0x1
XC1
XC1
0x2
XC2
XC2
0x3
EEVTEDG
External Event Edge Selection
8
2
read-write
NONE
None
0x0
RISING
Rising edge
0x1
FALLING
Falling edge
0x2
EDGE
Each edge
0x3
ENETRG
External Event Trigger Enable
12
1
read-write
TCCLKS
Clock Selection
0
3
read-write
TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x0
TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x1
TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x2
TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x3
TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x4
XC0
Clock selected: XC0
0x5
XC1
Clock selected: XC1
0x6
XC2
Clock selected: XC2
0x7
WAVE
Waveform Mode
15
1
read-write
WAVSEL
Waveform Selection
13
2
read-write
UP
UP mode without automatic trigger on RC Compare
0x0
UPDOWN
UPDOWN mode without automatic trigger on RC Compare
0x1
UP_RC
UP mode with automatic trigger on RC Compare
0x2
UPDOWN_RC
UPDOWN mode with automatic trigger on RC Compare
0x3
CMR1
Channel Mode Register (channel = 1)
0x44
32
read-write
n
0x0
0x0
ABETRG
TIOA or TIOB External Trigger Selection
10
1
read-write
BURST
Burst Signal Selection
4
2
read-write
NONE
The clock is not gated by an external signal.
0x0
XC0
XC0 is ANDed with the selected clock.
0x1
XC1
XC1 is ANDed with the selected clock.
0x2
XC2
XC2 is ANDed with the selected clock.
0x3
CLKI
Clock Invert
3
1
read-write
CPCTRG
RC Compare Trigger Enable
14
1
read-write
ETRGEDG
External Trigger Edge Selection
8
2
read-write
NONE
The clock is not gated by an external signal.
0x0
RISING
Rising edge
0x1
FALLING
Falling edge
0x2
EDGE
Each edge
0x3
LDBDIS
Counter Clock Disable with RB Loading
7
1
read-write
LDBSTOP
Counter Clock Stopped with RB Loading
6
1
read-write
LDRA
RA Loading Edge Selection
16
2
read-write
NONE
None
0x0
RISING
Rising edge of TIOA
0x1
FALLING
Falling edge of TIOA
0x2
EDGE
Each edge of TIOA
0x3
LDRB
RB Loading Edge Selection
18
2
read-write
NONE
None
0x0
RISING
Rising edge of TIOA
0x1
FALLING
Falling edge of TIOA
0x2
EDGE
Each edge of TIOA
0x3
TCCLKS
Clock Selection
0
3
read-write
TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x0
TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x1
TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x2
TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x3
TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x4
XC0
Clock selected: XC0
0x5
XC1
Clock selected: XC1
0x6
XC2
Clock selected: XC2
0x7
WAVE
Waveform Mode
15
1
read-write
CMR1_WAVE_EQ_1
Channel Mode Register (channel = 1)
WAVE_EQ_1
0x44
32
read-write
n
0x0
0x0
ACPA
RA Compare Effect on TIOA
16
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
ACPC
RC Compare Effect on TIOA
18
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
AEEVT
External Event Effect on TIOA
20
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
ASWTRG
Software Trigger Effect on TIOA
22
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BCPB
RB Compare Effect on TIOB
24
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BCPC
RC Compare Effect on TIOB
26
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BEEVT
External Event Effect on TIOB
28
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BSWTRG
Software Trigger Effect on TIOB
30
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BURST
Burst Signal Selection
4
2
read-write
NONE
The clock is not gated by an external signal.
0x0
XC0
XC0 is ANDed with the selected clock.
0x1
XC1
XC1 is ANDed with the selected clock.
0x2
XC2
XC2 is ANDed with the selected clock.
0x3
CLKI
Clock Invert
3
1
read-write
CPCDIS
Counter Clock Disable with RC Compare
7
1
read-write
CPCSTOP
Counter Clock Stopped with RC Compare
6
1
read-write
EEVT
External Event Selection
10
2
read-write
TIOB
TIOB
0x0
XC0
XC0
0x1
XC1
XC1
0x2
XC2
XC2
0x3
EEVTEDG
External Event Edge Selection
8
2
read-write
NONE
None
0x0
RISING
Rising edge
0x1
FALLING
Falling edge
0x2
EDGE
Each edge
0x3
ENETRG
External Event Trigger Enable
12
1
read-write
TCCLKS
Clock Selection
0
3
read-write
TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x0
TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x1
TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x2
TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x3
TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x4
XC0
Clock selected: XC0
0x5
XC1
Clock selected: XC1
0x6
XC2
Clock selected: XC2
0x7
WAVE
Waveform Mode
15
1
read-write
WAVSEL
Waveform Selection
13
2
read-write
UP
UP mode without automatic trigger on RC Compare
0x0
UPDOWN
UPDOWN mode without automatic trigger on RC Compare
0x1
UP_RC
UP mode with automatic trigger on RC Compare
0x2
UPDOWN_RC
UPDOWN mode with automatic trigger on RC Compare
0x3
CMR2
Channel Mode Register (channel = 2)
0x84
32
read-write
n
0x0
0x0
ABETRG
TIOA or TIOB External Trigger Selection
10
1
read-write
BURST
Burst Signal Selection
4
2
read-write
NONE
The clock is not gated by an external signal.
0x0
XC0
XC0 is ANDed with the selected clock.
0x1
XC1
XC1 is ANDed with the selected clock.
0x2
XC2
XC2 is ANDed with the selected clock.
0x3
CLKI
Clock Invert
3
1
read-write
CPCTRG
RC Compare Trigger Enable
14
1
read-write
ETRGEDG
External Trigger Edge Selection
8
2
read-write
NONE
The clock is not gated by an external signal.
0x0
RISING
Rising edge
0x1
FALLING
Falling edge
0x2
EDGE
Each edge
0x3
LDBDIS
Counter Clock Disable with RB Loading
7
1
read-write
LDBSTOP
Counter Clock Stopped with RB Loading
6
1
read-write
LDRA
RA Loading Edge Selection
16
2
read-write
NONE
None
0x0
RISING
Rising edge of TIOA
0x1
FALLING
Falling edge of TIOA
0x2
EDGE
Each edge of TIOA
0x3
LDRB
RB Loading Edge Selection
18
2
read-write
NONE
None
0x0
RISING
Rising edge of TIOA
0x1
FALLING
Falling edge of TIOA
0x2
EDGE
Each edge of TIOA
0x3
TCCLKS
Clock Selection
0
3
read-write
TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x0
TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x1
TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x2
TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x3
TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x4
XC0
Clock selected: XC0
0x5
XC1
Clock selected: XC1
0x6
XC2
Clock selected: XC2
0x7
WAVE
Waveform Mode
15
1
read-write
CMR2_WAVE_EQ_1
Channel Mode Register (channel = 2)
WAVE_EQ_1
0x84
32
read-write
n
0x0
0x0
ACPA
RA Compare Effect on TIOA
16
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
ACPC
RC Compare Effect on TIOA
18
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
AEEVT
External Event Effect on TIOA
20
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
ASWTRG
Software Trigger Effect on TIOA
22
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BCPB
RB Compare Effect on TIOB
24
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BCPC
RC Compare Effect on TIOB
26
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BEEVT
External Event Effect on TIOB
28
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BSWTRG
Software Trigger Effect on TIOB
30
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BURST
Burst Signal Selection
4
2
read-write
NONE
The clock is not gated by an external signal.
0x0
XC0
XC0 is ANDed with the selected clock.
0x1
XC1
XC1 is ANDed with the selected clock.
0x2
XC2
XC2 is ANDed with the selected clock.
0x3
CLKI
Clock Invert
3
1
read-write
CPCDIS
Counter Clock Disable with RC Compare
7
1
read-write
CPCSTOP
Counter Clock Stopped with RC Compare
6
1
read-write
EEVT
External Event Selection
10
2
read-write
TIOB
TIOB
0x0
XC0
XC0
0x1
XC1
XC1
0x2
XC2
XC2
0x3
EEVTEDG
External Event Edge Selection
8
2
read-write
NONE
None
0x0
RISING
Rising edge
0x1
FALLING
Falling edge
0x2
EDGE
Each edge
0x3
ENETRG
External Event Trigger Enable
12
1
read-write
TCCLKS
Clock Selection
0
3
read-write
TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x0
TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x1
TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x2
TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x3
TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x4
XC0
Clock selected: XC0
0x5
XC1
Clock selected: XC1
0x6
XC2
Clock selected: XC2
0x7
WAVE
Waveform Mode
15
1
read-write
WAVSEL
Waveform Selection
13
2
read-write
UP
UP mode without automatic trigger on RC Compare
0x0
UPDOWN
UPDOWN mode without automatic trigger on RC Compare
0x1
UP_RC
UP mode with automatic trigger on RC Compare
0x2
UPDOWN_RC
UPDOWN mode with automatic trigger on RC Compare
0x3
CV0
Counter Value (channel = 0)
0x10
32
read-only
n
0x0
0x0
CV
Counter Value
0
32
read-only
CV1
Counter Value (channel = 1)
0x50
32
read-only
n
0x0
0x0
CV
Counter Value
0
32
read-only
CV2
Counter Value (channel = 2)
0x90
32
read-only
n
0x0
0x0
CV
Counter Value
0
32
read-only
IDR0
Interrupt Disable Register (channel = 0)
0x28
32
write-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
write-only
CPAS
RA Compare
2
1
write-only
CPBS
RB Compare
3
1
write-only
CPCS
RC Compare
4
1
write-only
ETRGS
External Trigger
7
1
write-only
LDRAS
RA Loading
5
1
write-only
LDRBS
RB Loading
6
1
write-only
LOVRS
Load Overrun
1
1
write-only
IDR1
Interrupt Disable Register (channel = 1)
0x68
32
write-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
write-only
CPAS
RA Compare
2
1
write-only
CPBS
RB Compare
3
1
write-only
CPCS
RC Compare
4
1
write-only
ETRGS
External Trigger
7
1
write-only
LDRAS
RA Loading
5
1
write-only
LDRBS
RB Loading
6
1
write-only
LOVRS
Load Overrun
1
1
write-only
IDR2
Interrupt Disable Register (channel = 2)
0xA8
32
write-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
write-only
CPAS
RA Compare
2
1
write-only
CPBS
RB Compare
3
1
write-only
CPCS
RC Compare
4
1
write-only
ETRGS
External Trigger
7
1
write-only
LDRAS
RA Loading
5
1
write-only
LDRBS
RB Loading
6
1
write-only
LOVRS
Load Overrun
1
1
write-only
IER0
Interrupt Enable Register (channel = 0)
0x24
32
write-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
write-only
CPAS
RA Compare
2
1
write-only
CPBS
RB Compare
3
1
write-only
CPCS
RC Compare
4
1
write-only
ETRGS
External Trigger
7
1
write-only
LDRAS
RA Loading
5
1
write-only
LDRBS
RB Loading
6
1
write-only
LOVRS
Load Overrun
1
1
write-only
IER1
Interrupt Enable Register (channel = 1)
0x64
32
write-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
write-only
CPAS
RA Compare
2
1
write-only
CPBS
RB Compare
3
1
write-only
CPCS
RC Compare
4
1
write-only
ETRGS
External Trigger
7
1
write-only
LDRAS
RA Loading
5
1
write-only
LDRBS
RB Loading
6
1
write-only
LOVRS
Load Overrun
1
1
write-only
IER2
Interrupt Enable Register (channel = 2)
0xA4
32
write-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
write-only
CPAS
RA Compare
2
1
write-only
CPBS
RB Compare
3
1
write-only
CPCS
RC Compare
4
1
write-only
ETRGS
External Trigger
7
1
write-only
LDRAS
RA Loading
5
1
write-only
LDRBS
RB Loading
6
1
write-only
LOVRS
Load Overrun
1
1
write-only
IMR0
Interrupt Mask Register (channel = 0)
0x2C
32
read-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
read-only
CPAS
RA Compare
2
1
read-only
CPBS
RB Compare
3
1
read-only
CPCS
RC Compare
4
1
read-only
ETRGS
External Trigger
7
1
read-only
LDRAS
RA Loading
5
1
read-only
LDRBS
RB Loading
6
1
read-only
LOVRS
Load Overrun
1
1
read-only
IMR1
Interrupt Mask Register (channel = 1)
0x6C
32
read-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
read-only
CPAS
RA Compare
2
1
read-only
CPBS
RB Compare
3
1
read-only
CPCS
RC Compare
4
1
read-only
ETRGS
External Trigger
7
1
read-only
LDRAS
RA Loading
5
1
read-only
LDRBS
RB Loading
6
1
read-only
LOVRS
Load Overrun
1
1
read-only
IMR2
Interrupt Mask Register (channel = 2)
0xAC
32
read-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
read-only
CPAS
RA Compare
2
1
read-only
CPBS
RB Compare
3
1
read-only
CPCS
RC Compare
4
1
read-only
ETRGS
External Trigger
7
1
read-only
LDRAS
RA Loading
5
1
read-only
LDRBS
RB Loading
6
1
read-only
LOVRS
Load Overrun
1
1
read-only
QIDR
QDEC Interrupt Disable Register
0xCC
32
write-only
n
0x0
0x0
DIRCHG
Direction Change
1
1
write-only
IDX
Index
0
1
write-only
QERR
Quadrature Error
2
1
write-only
QIER
QDEC Interrupt Enable Register
0xC8
32
write-only
n
0x0
0x0
DIRCHG
Direction Change
1
1
write-only
IDX
Index
0
1
write-only
QERR
Quadrature Error
2
1
write-only
QIMR
QDEC Interrupt Mask Register
0xD0
32
read-only
n
0x0
0x0
DIRCHG
Direction Change
1
1
read-only
IDX
Index
0
1
read-only
QERR
Quadrature Error
2
1
read-only
QISR
QDEC Interrupt Status Register
0xD4
32
read-only
n
0x0
0x0
DIR
Direction
8
1
read-only
DIRCHG
Direction Change
1
1
read-only
IDX
Index
0
1
read-only
MPE
Consecutive Missing Pulse Error
3
1
read-only
QERR
Quadrature Error
2
1
read-only
RA0
Register A (channel = 0)
0x14
32
read-write
n
0x0
0x0
RA
Register A
0
32
read-write
RA1
Register A (channel = 1)
0x54
32
read-write
n
0x0
0x0
RA
Register A
0
32
read-write
RA2
Register A (channel = 2)
0x94
32
read-write
n
0x0
0x0
RA
Register A
0
32
read-write
RB0
Register B (channel = 0)
0x18
32
read-write
n
0x0
0x0
RB
Register B
0
32
read-write
RB1
Register B (channel = 1)
0x58
32
read-write
n
0x0
0x0
RB
Register B
0
32
read-write
RB2
Register B (channel = 2)
0x98
32
read-write
n
0x0
0x0
RB
Register B
0
32
read-write
RC0
Register C (channel = 0)
0x1C
32
read-write
n
0x0
0x0
RC
Register C
0
32
read-write
RC1
Register C (channel = 1)
0x5C
32
read-write
n
0x0
0x0
RC
Register C
0
32
read-write
RC2
Register C (channel = 2)
0x9C
32
read-write
n
0x0
0x0
RC
Register C
0
32
read-write
SMMR0
Stepper Motor Mode Register (channel = 0)
0x8
32
read-write
n
0x0
0x0
DOWN
Down Count
1
1
read-write
GCEN
Gray Count Enable
0
1
read-write
SMMR1
Stepper Motor Mode Register (channel = 1)
0x48
32
read-write
n
0x0
0x0
DOWN
Down Count
1
1
read-write
GCEN
Gray Count Enable
0
1
read-write
SMMR2
Stepper Motor Mode Register (channel = 2)
0x88
32
read-write
n
0x0
0x0
DOWN
Down Count
1
1
read-write
GCEN
Gray Count Enable
0
1
read-write
SR0
Status Register (channel = 0)
0x20
32
read-only
n
0x0
0x0
CLKSTA
Clock Enabling Status
16
1
read-only
COVFS
Counter Overflow Status
0
1
read-only
CPAS
RA Compare Status
2
1
read-only
CPBS
RB Compare Status
3
1
read-only
CPCS
RC Compare Status
4
1
read-only
ETRGS
External Trigger Status
7
1
read-only
LDRAS
RA Loading Status
5
1
read-only
LDRBS
RB Loading Status
6
1
read-only
LOVRS
Load Overrun Status
1
1
read-only
MTIOA
TIOA Mirror
17
1
read-only
MTIOB
TIOB Mirror
18
1
read-only
SR1
Status Register (channel = 1)
0x60
32
read-only
n
0x0
0x0
CLKSTA
Clock Enabling Status
16
1
read-only
COVFS
Counter Overflow Status
0
1
read-only
CPAS
RA Compare Status
2
1
read-only
CPBS
RB Compare Status
3
1
read-only
CPCS
RC Compare Status
4
1
read-only
ETRGS
External Trigger Status
7
1
read-only
LDRAS
RA Loading Status
5
1
read-only
LDRBS
RB Loading Status
6
1
read-only
LOVRS
Load Overrun Status
1
1
read-only
MTIOA
TIOA Mirror
17
1
read-only
MTIOB
TIOB Mirror
18
1
read-only
SR2
Status Register (channel = 2)
0xA0
32
read-only
n
0x0
0x0
CLKSTA
Clock Enabling Status
16
1
read-only
COVFS
Counter Overflow Status
0
1
read-only
CPAS
RA Compare Status
2
1
read-only
CPBS
RB Compare Status
3
1
read-only
CPCS
RC Compare Status
4
1
read-only
ETRGS
External Trigger Status
7
1
read-only
LDRAS
RA Loading Status
5
1
read-only
LDRBS
RB Loading Status
6
1
read-only
LOVRS
Load Overrun Status
1
1
read-only
MTIOA
TIOA Mirror
17
1
read-only
MTIOB
TIOB Mirror
18
1
read-only
WPMR
Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protection Enable
0
1
read-write
WPKEY
Write Protection Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
0x54494D
TC1
Timer Counter 1
TC
0x0
0x0
0x50
registers
n
TC3
26
TC4
27
TC5
28
BCR
Block Control Register
0xC0
32
write-only
n
0x0
0x0
SYNC
Synchro Command
0
1
write-only
BMR
Block Mode Register
0xC4
32
read-write
n
0x0
0x0
AUTOC
Auto-Correction of missing pulses
18
1
read-write
DISABLED
The detection and auto-correction function is disabled.
0
ENABLED
The detection and auto-correction function is enabled.
1
EDGPHA
Edge on PHA Count Mode
12
1
read-write
IDXPHB
Index Pin is PHB Pin
17
1
read-write
INVA
Inverted PHA
13
1
read-write
INVB
Inverted PHB
14
1
read-write
INVIDX
Inverted Index
15
1
read-write
MAXCMP
Maximum Consecutive Missing Pulses
26
4
read-write
MAXFILT
Maximum Filter
20
6
read-write
POSEN
Position Enabled
9
1
read-write
QDEN
Quadrature Decoder Enabled
8
1
read-write
QDTRANS
Quadrature Decoding Transparent
11
1
read-write
SPEEDEN
Speed Enabled
10
1
read-write
SWAP
Swap PHA and PHB
16
1
read-write
TC0XC0S
External Clock Signal 0 Selection
0
2
read-write
TCLK0
Signal connected to XC0: TCLK0
0x0
TIOA1
Signal connected to XC0: TIOA1
0x2
TIOA2
Signal connected to XC0: TIOA2
0x3
TC1XC1S
External Clock Signal 1 Selection
2
2
read-write
TCLK1
Signal connected to XC1: TCLK1
0x0
TIOA0
Signal connected to XC1: TIOA0
0x2
TIOA2
Signal connected to XC1: TIOA2
0x3
TC2XC2S
External Clock Signal 2 Selection
4
2
read-write
TCLK2
Signal connected to XC2: TCLK2
0x0
TIOA0
Signal connected to XC2: TIOA0
0x2
TIOA1
Signal connected to XC2: TIOA1
0x3
CCR0
Channel Control Register (channel = 0)
0x0
32
write-only
n
0x0
0x0
CLKDIS
Counter Clock Disable Command
1
1
write-only
CLKEN
Counter Clock Enable Command
0
1
write-only
SWTRG
Software Trigger Command
2
1
write-only
CCR1
Channel Control Register (channel = 1)
0x40
32
write-only
n
0x0
0x0
CLKDIS
Counter Clock Disable Command
1
1
write-only
CLKEN
Counter Clock Enable Command
0
1
write-only
SWTRG
Software Trigger Command
2
1
write-only
CCR2
Channel Control Register (channel = 2)
0x80
32
write-only
n
0x0
0x0
CLKDIS
Counter Clock Disable Command
1
1
write-only
CLKEN
Counter Clock Enable Command
0
1
write-only
SWTRG
Software Trigger Command
2
1
write-only
CMR0
Channel Mode Register (channel = 0)
0x4
32
read-write
n
0x0
0x0
ABETRG
TIOA or TIOB External Trigger Selection
10
1
read-write
BURST
Burst Signal Selection
4
2
read-write
NONE
The clock is not gated by an external signal.
0x0
XC0
XC0 is ANDed with the selected clock.
0x1
XC1
XC1 is ANDed with the selected clock.
0x2
XC2
XC2 is ANDed with the selected clock.
0x3
CLKI
Clock Invert
3
1
read-write
CPCTRG
RC Compare Trigger Enable
14
1
read-write
ETRGEDG
External Trigger Edge Selection
8
2
read-write
NONE
The clock is not gated by an external signal.
0x0
RISING
Rising edge
0x1
FALLING
Falling edge
0x2
EDGE
Each edge
0x3
LDBDIS
Counter Clock Disable with RB Loading
7
1
read-write
LDBSTOP
Counter Clock Stopped with RB Loading
6
1
read-write
LDRA
RA Loading Edge Selection
16
2
read-write
NONE
None
0x0
RISING
Rising edge of TIOA
0x1
FALLING
Falling edge of TIOA
0x2
EDGE
Each edge of TIOA
0x3
LDRB
RB Loading Edge Selection
18
2
read-write
NONE
None
0x0
RISING
Rising edge of TIOA
0x1
FALLING
Falling edge of TIOA
0x2
EDGE
Each edge of TIOA
0x3
TCCLKS
Clock Selection
0
3
read-write
TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x0
TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x1
TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x2
TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x3
TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x4
XC0
Clock selected: XC0
0x5
XC1
Clock selected: XC1
0x6
XC2
Clock selected: XC2
0x7
WAVE
Waveform Mode
15
1
read-write
CMR0_WAVE_EQ_1
Channel Mode Register (channel = 0)
WAVE_EQ_1
0x4
32
read-write
n
0x0
0x0
ACPA
RA Compare Effect on TIOA
16
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
ACPC
RC Compare Effect on TIOA
18
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
AEEVT
External Event Effect on TIOA
20
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
ASWTRG
Software Trigger Effect on TIOA
22
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BCPB
RB Compare Effect on TIOB
24
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BCPC
RC Compare Effect on TIOB
26
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BEEVT
External Event Effect on TIOB
28
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BSWTRG
Software Trigger Effect on TIOB
30
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BURST
Burst Signal Selection
4
2
read-write
NONE
The clock is not gated by an external signal.
0x0
XC0
XC0 is ANDed with the selected clock.
0x1
XC1
XC1 is ANDed with the selected clock.
0x2
XC2
XC2 is ANDed with the selected clock.
0x3
CLKI
Clock Invert
3
1
read-write
CPCDIS
Counter Clock Disable with RC Compare
7
1
read-write
CPCSTOP
Counter Clock Stopped with RC Compare
6
1
read-write
EEVT
External Event Selection
10
2
read-write
TIOB
TIOB
0x0
XC0
XC0
0x1
XC1
XC1
0x2
XC2
XC2
0x3
EEVTEDG
External Event Edge Selection
8
2
read-write
NONE
None
0x0
RISING
Rising edge
0x1
FALLING
Falling edge
0x2
EDGE
Each edge
0x3
ENETRG
External Event Trigger Enable
12
1
read-write
TCCLKS
Clock Selection
0
3
read-write
TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x0
TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x1
TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x2
TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x3
TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x4
XC0
Clock selected: XC0
0x5
XC1
Clock selected: XC1
0x6
XC2
Clock selected: XC2
0x7
WAVE
Waveform Mode
15
1
read-write
WAVSEL
Waveform Selection
13
2
read-write
UP
UP mode without automatic trigger on RC Compare
0x0
UPDOWN
UPDOWN mode without automatic trigger on RC Compare
0x1
UP_RC
UP mode with automatic trigger on RC Compare
0x2
UPDOWN_RC
UPDOWN mode with automatic trigger on RC Compare
0x3
CMR1
Channel Mode Register (channel = 1)
0x44
32
read-write
n
0x0
0x0
ABETRG
TIOA or TIOB External Trigger Selection
10
1
read-write
BURST
Burst Signal Selection
4
2
read-write
NONE
The clock is not gated by an external signal.
0x0
XC0
XC0 is ANDed with the selected clock.
0x1
XC1
XC1 is ANDed with the selected clock.
0x2
XC2
XC2 is ANDed with the selected clock.
0x3
CLKI
Clock Invert
3
1
read-write
CPCTRG
RC Compare Trigger Enable
14
1
read-write
ETRGEDG
External Trigger Edge Selection
8
2
read-write
NONE
The clock is not gated by an external signal.
0x0
RISING
Rising edge
0x1
FALLING
Falling edge
0x2
EDGE
Each edge
0x3
LDBDIS
Counter Clock Disable with RB Loading
7
1
read-write
LDBSTOP
Counter Clock Stopped with RB Loading
6
1
read-write
LDRA
RA Loading Edge Selection
16
2
read-write
NONE
None
0x0
RISING
Rising edge of TIOA
0x1
FALLING
Falling edge of TIOA
0x2
EDGE
Each edge of TIOA
0x3
LDRB
RB Loading Edge Selection
18
2
read-write
NONE
None
0x0
RISING
Rising edge of TIOA
0x1
FALLING
Falling edge of TIOA
0x2
EDGE
Each edge of TIOA
0x3
TCCLKS
Clock Selection
0
3
read-write
TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x0
TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x1
TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x2
TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x3
TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x4
XC0
Clock selected: XC0
0x5
XC1
Clock selected: XC1
0x6
XC2
Clock selected: XC2
0x7
WAVE
Waveform Mode
15
1
read-write
CMR1_WAVE_EQ_1
Channel Mode Register (channel = 1)
WAVE_EQ_1
0x44
32
read-write
n
0x0
0x0
ACPA
RA Compare Effect on TIOA
16
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
ACPC
RC Compare Effect on TIOA
18
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
AEEVT
External Event Effect on TIOA
20
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
ASWTRG
Software Trigger Effect on TIOA
22
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BCPB
RB Compare Effect on TIOB
24
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BCPC
RC Compare Effect on TIOB
26
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BEEVT
External Event Effect on TIOB
28
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BSWTRG
Software Trigger Effect on TIOB
30
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BURST
Burst Signal Selection
4
2
read-write
NONE
The clock is not gated by an external signal.
0x0
XC0
XC0 is ANDed with the selected clock.
0x1
XC1
XC1 is ANDed with the selected clock.
0x2
XC2
XC2 is ANDed with the selected clock.
0x3
CLKI
Clock Invert
3
1
read-write
CPCDIS
Counter Clock Disable with RC Compare
7
1
read-write
CPCSTOP
Counter Clock Stopped with RC Compare
6
1
read-write
EEVT
External Event Selection
10
2
read-write
TIOB
TIOB
0x0
XC0
XC0
0x1
XC1
XC1
0x2
XC2
XC2
0x3
EEVTEDG
External Event Edge Selection
8
2
read-write
NONE
None
0x0
RISING
Rising edge
0x1
FALLING
Falling edge
0x2
EDGE
Each edge
0x3
ENETRG
External Event Trigger Enable
12
1
read-write
TCCLKS
Clock Selection
0
3
read-write
TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x0
TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x1
TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x2
TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x3
TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x4
XC0
Clock selected: XC0
0x5
XC1
Clock selected: XC1
0x6
XC2
Clock selected: XC2
0x7
WAVE
Waveform Mode
15
1
read-write
WAVSEL
Waveform Selection
13
2
read-write
UP
UP mode without automatic trigger on RC Compare
0x0
UPDOWN
UPDOWN mode without automatic trigger on RC Compare
0x1
UP_RC
UP mode with automatic trigger on RC Compare
0x2
UPDOWN_RC
UPDOWN mode with automatic trigger on RC Compare
0x3
CMR2
Channel Mode Register (channel = 2)
0x84
32
read-write
n
0x0
0x0
ABETRG
TIOA or TIOB External Trigger Selection
10
1
read-write
BURST
Burst Signal Selection
4
2
read-write
NONE
The clock is not gated by an external signal.
0x0
XC0
XC0 is ANDed with the selected clock.
0x1
XC1
XC1 is ANDed with the selected clock.
0x2
XC2
XC2 is ANDed with the selected clock.
0x3
CLKI
Clock Invert
3
1
read-write
CPCTRG
RC Compare Trigger Enable
14
1
read-write
ETRGEDG
External Trigger Edge Selection
8
2
read-write
NONE
The clock is not gated by an external signal.
0x0
RISING
Rising edge
0x1
FALLING
Falling edge
0x2
EDGE
Each edge
0x3
LDBDIS
Counter Clock Disable with RB Loading
7
1
read-write
LDBSTOP
Counter Clock Stopped with RB Loading
6
1
read-write
LDRA
RA Loading Edge Selection
16
2
read-write
NONE
None
0x0
RISING
Rising edge of TIOA
0x1
FALLING
Falling edge of TIOA
0x2
EDGE
Each edge of TIOA
0x3
LDRB
RB Loading Edge Selection
18
2
read-write
NONE
None
0x0
RISING
Rising edge of TIOA
0x1
FALLING
Falling edge of TIOA
0x2
EDGE
Each edge of TIOA
0x3
TCCLKS
Clock Selection
0
3
read-write
TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x0
TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x1
TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x2
TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x3
TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x4
XC0
Clock selected: XC0
0x5
XC1
Clock selected: XC1
0x6
XC2
Clock selected: XC2
0x7
WAVE
Waveform Mode
15
1
read-write
CMR2_WAVE_EQ_1
Channel Mode Register (channel = 2)
WAVE_EQ_1
0x84
32
read-write
n
0x0
0x0
ACPA
RA Compare Effect on TIOA
16
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
ACPC
RC Compare Effect on TIOA
18
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
AEEVT
External Event Effect on TIOA
20
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
ASWTRG
Software Trigger Effect on TIOA
22
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BCPB
RB Compare Effect on TIOB
24
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BCPC
RC Compare Effect on TIOB
26
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BEEVT
External Event Effect on TIOB
28
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BSWTRG
Software Trigger Effect on TIOB
30
2
read-write
NONE
None
0x0
SET
Set
0x1
CLEAR
Clear
0x2
TOGGLE
Toggle
0x3
BURST
Burst Signal Selection
4
2
read-write
NONE
The clock is not gated by an external signal.
0x0
XC0
XC0 is ANDed with the selected clock.
0x1
XC1
XC1 is ANDed with the selected clock.
0x2
XC2
XC2 is ANDed with the selected clock.
0x3
CLKI
Clock Invert
3
1
read-write
CPCDIS
Counter Clock Disable with RC Compare
7
1
read-write
CPCSTOP
Counter Clock Stopped with RC Compare
6
1
read-write
EEVT
External Event Selection
10
2
read-write
TIOB
TIOB
0x0
XC0
XC0
0x1
XC1
XC1
0x2
XC2
XC2
0x3
EEVTEDG
External Event Edge Selection
8
2
read-write
NONE
None
0x0
RISING
Rising edge
0x1
FALLING
Falling edge
0x2
EDGE
Each edge
0x3
ENETRG
External Event Trigger Enable
12
1
read-write
TCCLKS
Clock Selection
0
3
read-write
TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x0
TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x1
TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x2
TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x3
TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x4
XC0
Clock selected: XC0
0x5
XC1
Clock selected: XC1
0x6
XC2
Clock selected: XC2
0x7
WAVE
Waveform Mode
15
1
read-write
WAVSEL
Waveform Selection
13
2
read-write
UP
UP mode without automatic trigger on RC Compare
0x0
UPDOWN
UPDOWN mode without automatic trigger on RC Compare
0x1
UP_RC
UP mode with automatic trigger on RC Compare
0x2
UPDOWN_RC
UPDOWN mode with automatic trigger on RC Compare
0x3
CV0
Counter Value (channel = 0)
0x10
32
read-only
n
0x0
0x0
CV
Counter Value
0
32
read-only
CV1
Counter Value (channel = 1)
0x50
32
read-only
n
0x0
0x0
CV
Counter Value
0
32
read-only
CV2
Counter Value (channel = 2)
0x90
32
read-only
n
0x0
0x0
CV
Counter Value
0
32
read-only
IDR0
Interrupt Disable Register (channel = 0)
0x28
32
write-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
write-only
CPAS
RA Compare
2
1
write-only
CPBS
RB Compare
3
1
write-only
CPCS
RC Compare
4
1
write-only
ETRGS
External Trigger
7
1
write-only
LDRAS
RA Loading
5
1
write-only
LDRBS
RB Loading
6
1
write-only
LOVRS
Load Overrun
1
1
write-only
IDR1
Interrupt Disable Register (channel = 1)
0x68
32
write-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
write-only
CPAS
RA Compare
2
1
write-only
CPBS
RB Compare
3
1
write-only
CPCS
RC Compare
4
1
write-only
ETRGS
External Trigger
7
1
write-only
LDRAS
RA Loading
5
1
write-only
LDRBS
RB Loading
6
1
write-only
LOVRS
Load Overrun
1
1
write-only
IDR2
Interrupt Disable Register (channel = 2)
0xA8
32
write-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
write-only
CPAS
RA Compare
2
1
write-only
CPBS
RB Compare
3
1
write-only
CPCS
RC Compare
4
1
write-only
ETRGS
External Trigger
7
1
write-only
LDRAS
RA Loading
5
1
write-only
LDRBS
RB Loading
6
1
write-only
LOVRS
Load Overrun
1
1
write-only
IER0
Interrupt Enable Register (channel = 0)
0x24
32
write-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
write-only
CPAS
RA Compare
2
1
write-only
CPBS
RB Compare
3
1
write-only
CPCS
RC Compare
4
1
write-only
ETRGS
External Trigger
7
1
write-only
LDRAS
RA Loading
5
1
write-only
LDRBS
RB Loading
6
1
write-only
LOVRS
Load Overrun
1
1
write-only
IER1
Interrupt Enable Register (channel = 1)
0x64
32
write-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
write-only
CPAS
RA Compare
2
1
write-only
CPBS
RB Compare
3
1
write-only
CPCS
RC Compare
4
1
write-only
ETRGS
External Trigger
7
1
write-only
LDRAS
RA Loading
5
1
write-only
LDRBS
RB Loading
6
1
write-only
LOVRS
Load Overrun
1
1
write-only
IER2
Interrupt Enable Register (channel = 2)
0xA4
32
write-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
write-only
CPAS
RA Compare
2
1
write-only
CPBS
RB Compare
3
1
write-only
CPCS
RC Compare
4
1
write-only
ETRGS
External Trigger
7
1
write-only
LDRAS
RA Loading
5
1
write-only
LDRBS
RB Loading
6
1
write-only
LOVRS
Load Overrun
1
1
write-only
IMR0
Interrupt Mask Register (channel = 0)
0x2C
32
read-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
read-only
CPAS
RA Compare
2
1
read-only
CPBS
RB Compare
3
1
read-only
CPCS
RC Compare
4
1
read-only
ETRGS
External Trigger
7
1
read-only
LDRAS
RA Loading
5
1
read-only
LDRBS
RB Loading
6
1
read-only
LOVRS
Load Overrun
1
1
read-only
IMR1
Interrupt Mask Register (channel = 1)
0x6C
32
read-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
read-only
CPAS
RA Compare
2
1
read-only
CPBS
RB Compare
3
1
read-only
CPCS
RC Compare
4
1
read-only
ETRGS
External Trigger
7
1
read-only
LDRAS
RA Loading
5
1
read-only
LDRBS
RB Loading
6
1
read-only
LOVRS
Load Overrun
1
1
read-only
IMR2
Interrupt Mask Register (channel = 2)
0xAC
32
read-only
n
0x0
0x0
COVFS
Counter Overflow
0
1
read-only
CPAS
RA Compare
2
1
read-only
CPBS
RB Compare
3
1
read-only
CPCS
RC Compare
4
1
read-only
ETRGS
External Trigger
7
1
read-only
LDRAS
RA Loading
5
1
read-only
LDRBS
RB Loading
6
1
read-only
LOVRS
Load Overrun
1
1
read-only
QIDR
QDEC Interrupt Disable Register
0xCC
32
write-only
n
0x0
0x0
DIRCHG
Direction Change
1
1
write-only
IDX
Index
0
1
write-only
QERR
Quadrature Error
2
1
write-only
QIER
QDEC Interrupt Enable Register
0xC8
32
write-only
n
0x0
0x0
DIRCHG
Direction Change
1
1
write-only
IDX
Index
0
1
write-only
QERR
Quadrature Error
2
1
write-only
QIMR
QDEC Interrupt Mask Register
0xD0
32
read-only
n
0x0
0x0
DIRCHG
Direction Change
1
1
read-only
IDX
Index
0
1
read-only
QERR
Quadrature Error
2
1
read-only
QISR
QDEC Interrupt Status Register
0xD4
32
read-only
n
0x0
0x0
DIR
Direction
8
1
read-only
DIRCHG
Direction Change
1
1
read-only
IDX
Index
0
1
read-only
MPE
Consecutive Missing Pulse Error
3
1
read-only
QERR
Quadrature Error
2
1
read-only
RA0
Register A (channel = 0)
0x14
32
read-write
n
0x0
0x0
RA
Register A
0
32
read-write
RA1
Register A (channel = 1)
0x54
32
read-write
n
0x0
0x0
RA
Register A
0
32
read-write
RA2
Register A (channel = 2)
0x94
32
read-write
n
0x0
0x0
RA
Register A
0
32
read-write
RB0
Register B (channel = 0)
0x18
32
read-write
n
0x0
0x0
RB
Register B
0
32
read-write
RB1
Register B (channel = 1)
0x58
32
read-write
n
0x0
0x0
RB
Register B
0
32
read-write
RB2
Register B (channel = 2)
0x98
32
read-write
n
0x0
0x0
RB
Register B
0
32
read-write
RC0
Register C (channel = 0)
0x1C
32
read-write
n
0x0
0x0
RC
Register C
0
32
read-write
RC1
Register C (channel = 1)
0x5C
32
read-write
n
0x0
0x0
RC
Register C
0
32
read-write
RC2
Register C (channel = 2)
0x9C
32
read-write
n
0x0
0x0
RC
Register C
0
32
read-write
SMMR0
Stepper Motor Mode Register (channel = 0)
0x8
32
read-write
n
0x0
0x0
DOWN
Down Count
1
1
read-write
GCEN
Gray Count Enable
0
1
read-write
SMMR1
Stepper Motor Mode Register (channel = 1)
0x48
32
read-write
n
0x0
0x0
DOWN
Down Count
1
1
read-write
GCEN
Gray Count Enable
0
1
read-write
SMMR2
Stepper Motor Mode Register (channel = 2)
0x88
32
read-write
n
0x0
0x0
DOWN
Down Count
1
1
read-write
GCEN
Gray Count Enable
0
1
read-write
SR0
Status Register (channel = 0)
0x20
32
read-only
n
0x0
0x0
CLKSTA
Clock Enabling Status
16
1
read-only
COVFS
Counter Overflow Status
0
1
read-only
CPAS
RA Compare Status
2
1
read-only
CPBS
RB Compare Status
3
1
read-only
CPCS
RC Compare Status
4
1
read-only
ETRGS
External Trigger Status
7
1
read-only
LDRAS
RA Loading Status
5
1
read-only
LDRBS
RB Loading Status
6
1
read-only
LOVRS
Load Overrun Status
1
1
read-only
MTIOA
TIOA Mirror
17
1
read-only
MTIOB
TIOB Mirror
18
1
read-only
SR1
Status Register (channel = 1)
0x60
32
read-only
n
0x0
0x0
CLKSTA
Clock Enabling Status
16
1
read-only
COVFS
Counter Overflow Status
0
1
read-only
CPAS
RA Compare Status
2
1
read-only
CPBS
RB Compare Status
3
1
read-only
CPCS
RC Compare Status
4
1
read-only
ETRGS
External Trigger Status
7
1
read-only
LDRAS
RA Loading Status
5
1
read-only
LDRBS
RB Loading Status
6
1
read-only
LOVRS
Load Overrun Status
1
1
read-only
MTIOA
TIOA Mirror
17
1
read-only
MTIOB
TIOB Mirror
18
1
read-only
SR2
Status Register (channel = 2)
0xA0
32
read-only
n
0x0
0x0
CLKSTA
Clock Enabling Status
16
1
read-only
COVFS
Counter Overflow Status
0
1
read-only
CPAS
RA Compare Status
2
1
read-only
CPBS
RB Compare Status
3
1
read-only
CPCS
RC Compare Status
4
1
read-only
ETRGS
External Trigger Status
7
1
read-only
LDRAS
RA Loading Status
5
1
read-only
LDRBS
RB Loading Status
6
1
read-only
LOVRS
Load Overrun Status
1
1
read-only
MTIOA
TIOA Mirror
17
1
read-only
MTIOB
TIOB Mirror
18
1
read-only
WPMR
Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protection Enable
0
1
read-write
WPKEY
Write Protection Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
0x54494D
TRNG
True Random Number Generator
TRNG
0x0
0x0
0x50
registers
n
TRNG
33
CR
Control Register
0x0
32
write-only
n
0x0
0x0
ENABLE
Enables the TRNG to provide random values
0
1
write-only
KEY
Security Key.
8
24
write-only
PASSWD
Writing any other value in this field aborts the write operation.
0x524E47
IDR
Interrupt Disable Register
0x14
32
write-only
n
0x0
0x0
DATRDY
Data Ready Interrupt Disable
0
1
write-only
IER
Interrupt Enable Register
0x10
32
write-only
n
0x0
0x0
DATRDY
Data Ready Interrupt Enable
0
1
write-only
IMR
Interrupt Mask Register
0x18
32
read-only
n
0x0
0x0
DATRDY
Data Ready Interrupt Mask
0
1
read-only
ISR
Interrupt Status Register
0x1C
32
read-only
n
0x0
0x0
DATRDY
Data Ready
0
1
read-only
ODATA
Output Data Register
0x50
32
read-only
n
0x0
0x0
ODATA
Output Data
0
32
read-only
TWI0
Two-wire Interface 0
TWI
0x0
0x0
0x50
registers
n
TWI0
19
CR
Control Register
0x0
32
write-only
n
0x0
0x0
MSDIS
TWI Master Mode Disabled
3
1
write-only
MSEN
TWI Master Mode Enabled
2
1
write-only
QUICK
SMBus Quick Command
6
1
write-only
START
Send a START Condition
0
1
write-only
STOP
Send a STOP Condition
1
1
write-only
SVDIS
TWI Slave Mode Disabled
5
1
write-only
SVEN
TWI Slave Mode Enabled
4
1
write-only
SWRST
Software Reset
7
1
write-only
CWGR
Clock Waveform Generator Register
0x10
32
read-write
n
0x0
0x0
CHDIV
Clock High Divider
8
8
read-write
CKDIV
Clock Divider
16
3
read-write
CLDIV
Clock Low Divider
0
8
read-write
IADR
Internal Address Register
0xC
32
read-write
n
0x0
0x0
IADR
Internal Address
0
24
read-write
IDR
Interrupt Disable Register
0x28
32
write-only
n
0x0
0x0
ARBLST
Arbitration Lost Interrupt Disable
9
1
write-only
ENDRX
End of Receive Buffer Interrupt Disable
12
1
write-only
ENDTX
End of Transmit Buffer Interrupt Disable
13
1
write-only
EOSACC
End Of Slave Access Interrupt Disable
11
1
write-only
GACC
General Call Access Interrupt Disable
5
1
write-only
NACK
Not Acknowledge Interrupt Disable
8
1
write-only
OVRE
Overrun Error Interrupt Disable
6
1
write-only
RXBUFF
Receive Buffer Full Interrupt Disable
14
1
write-only
RXRDY
Receive Holding Register Ready Interrupt Disable
1
1
write-only
SCL_WS
Clock Wait State Interrupt Disable
10
1
write-only
SVACC
Slave Access Interrupt Disable
4
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Disable
15
1
write-only
TXCOMP
Transmission Completed Interrupt Disable
0
1
write-only
TXRDY
Transmit Holding Register Ready Interrupt Disable
2
1
write-only
IER
Interrupt Enable Register
0x24
32
write-only
n
0x0
0x0
ARBLST
Arbitration Lost Interrupt Enable
9
1
write-only
ENDRX
End of Receive Buffer Interrupt Enable
12
1
write-only
ENDTX
End of Transmit Buffer Interrupt Enable
13
1
write-only
EOSACC
End Of Slave Access Interrupt Enable
11
1
write-only
GACC
General Call Access Interrupt Enable
5
1
write-only
NACK
Not Acknowledge Interrupt Enable
8
1
write-only
OVRE
Overrun Error Interrupt Enable
6
1
write-only
RXBUFF
Receive Buffer Full Interrupt Enable
14
1
write-only
RXRDY
Receive Holding Register Ready Interrupt Enable
1
1
write-only
SCL_WS
Clock Wait State Interrupt Enable
10
1
write-only
SVACC
Slave Access Interrupt Enable
4
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Enable
15
1
write-only
TXCOMP
Transmission Completed Interrupt Enable
0
1
write-only
TXRDY
Transmit Holding Register Ready Interrupt Enable
2
1
write-only
IMR
Interrupt Mask Register
0x2C
32
read-only
n
0x0
0x0
ARBLST
Arbitration Lost Interrupt Mask
9
1
read-only
ENDRX
End of Receive Buffer Interrupt Mask
12
1
read-only
ENDTX
End of Transmit Buffer Interrupt Mask
13
1
read-only
EOSACC
End Of Slave Access Interrupt Mask
11
1
read-only
GACC
General Call Access Interrupt Mask
5
1
read-only
NACK
Not Acknowledge Interrupt Mask
8
1
read-only
OVRE
Overrun Error Interrupt Mask
6
1
read-only
RXBUFF
Receive Buffer Full Interrupt Mask
14
1
read-only
RXRDY
Receive Holding Register Ready Interrupt Mask
1
1
read-only
SCL_WS
Clock Wait State Interrupt Mask
10
1
read-only
SVACC
Slave Access Interrupt Mask
4
1
read-only
TXBUFE
Transmit Buffer Empty Interrupt Mask
15
1
read-only
TXCOMP
Transmission Completed Interrupt Mask
0
1
read-only
TXRDY
Transmit Holding Register Ready Interrupt Mask
2
1
read-only
MMR
Master Mode Register
0x4
32
read-write
n
0x0
0x0
DADR
Device Address
16
7
read-write
IADRSZ
Internal Device Address Size
8
2
read-write
NONE
No internal device address
0x0
1_BYTE
One-byte internal device address
0x1
2_BYTE
Two-byte internal device address
0x2
3_BYTE
Three-byte internal device address
0x3
MREAD
Master Read Direction
12
1
read-write
PTCR
Transfer Control Register
0x120
32
write-only
n
0x0
0x0
RXTDIS
Receiver Transfer Disable
1
1
write-only
RXTEN
Receiver Transfer Enable
0
1
write-only
TXTDIS
Transmitter Transfer Disable
9
1
write-only
TXTEN
Transmitter Transfer Enable
8
1
write-only
PTSR
Transfer Status Register
0x124
32
read-only
n
0x0
0x0
RXTEN
Receiver Transfer Enable
0
1
read-only
TXTEN
Transmitter Transfer Enable
8
1
read-only
RCR
Receive Counter Register
0x104
32
read-write
n
0x0
0x0
RXCTR
Receive Counter Register
0
16
read-write
RHR
Receive Holding Register
0x30
32
read-only
n
0x0
0x0
RXDATA
Master or Slave Receive Holding Data
0
8
read-only
RNCR
Receive Next Counter Register
0x114
32
read-write
n
0x0
0x0
RXNCTR
Receive Next Counter
0
16
read-write
RNPR
Receive Next Pointer Register
0x110
32
read-write
n
0x0
0x0
RXNPTR
Receive Next Pointer
0
32
read-write
RPR
Receive Pointer Register
0x100
32
read-write
n
0x0
0x0
RXPTR
Receive Pointer Register
0
32
read-write
SMR
Slave Mode Register
0x8
32
read-write
n
0x0
0x0
SADR
Slave Address
16
7
read-write
SR
Status Register
0x20
32
read-only
n
0x0
0x0
ARBLST
Arbitration Lost (clear on read)
9
1
read-only
ENDRX
End of RX buffer
12
1
read-only
ENDTX
End of TX buffer
13
1
read-only
EOSACC
End Of Slave Access (clear on read)
11
1
read-only
GACC
General Call Access (clear on read)
5
1
read-only
NACK
Not Acknowledged (clear on read)
8
1
read-only
OVRE
Overrun Error (clear on read)
6
1
read-only
RXBUFF
RX Buffer Full
14
1
read-only
RXRDY
Receive Holding Register Ready (automatically set / reset)
1
1
read-only
SCLWS
Clock Wait State (automatically set / reset)
10
1
read-only
SVACC
Slave Access (automatically set / reset)
4
1
read-only
SVREAD
Slave Read (automatically set / reset)
3
1
read-only
TXBUFE
TX Buffer Empty
15
1
read-only
TXCOMP
Transmission Completed (automatically set / reset)
0
1
read-only
TXRDY
Transmit Holding Register Ready (automatically set / reset)
2
1
read-only
TCR
Transmit Counter Register
0x10C
32
read-write
n
0x0
0x0
TXCTR
Transmit Counter Register
0
16
read-write
THR
Transmit Holding Register
0x34
32
write-only
n
0x0
0x0
TXDATA
Master or Slave Transmit Holding Data
0
8
write-only
TNCR
Transmit Next Counter Register
0x11C
32
read-write
n
0x0
0x0
TXNCTR
Transmit Counter Next
0
16
read-write
TNPR
Transmit Next Pointer Register
0x118
32
read-write
n
0x0
0x0
TXNPTR
Transmit Next Pointer
0
32
read-write
TPR
Transmit Pointer Register
0x108
32
read-write
n
0x0
0x0
TXPTR
Transmit Counter Register
0
32
read-write
WPMR
Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protection Enable
0
1
read-write
WPKEY
Write Protection Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0
0x545749
WPSR
Write Protection Status Register
0xE8
32
read-only
n
0x0
0x0
WPVS
Write Protection Violation Status
0
1
read-only
WPVSRC
Write Protection Violation Source
8
24
read-only
TWI1
Two-wire Interface 1
TWI
0x0
0x0
0x50
registers
n
TWI1
20
CR
Control Register
0x0
32
write-only
n
0x0
0x0
MSDIS
TWI Master Mode Disabled
3
1
write-only
MSEN
TWI Master Mode Enabled
2
1
write-only
QUICK
SMBus Quick Command
6
1
write-only
START
Send a START Condition
0
1
write-only
STOP
Send a STOP Condition
1
1
write-only
SVDIS
TWI Slave Mode Disabled
5
1
write-only
SVEN
TWI Slave Mode Enabled
4
1
write-only
SWRST
Software Reset
7
1
write-only
CWGR
Clock Waveform Generator Register
0x10
32
read-write
n
0x0
0x0
CHDIV
Clock High Divider
8
8
read-write
CKDIV
Clock Divider
16
3
read-write
CLDIV
Clock Low Divider
0
8
read-write
IADR
Internal Address Register
0xC
32
read-write
n
0x0
0x0
IADR
Internal Address
0
24
read-write
IDR
Interrupt Disable Register
0x28
32
write-only
n
0x0
0x0
ARBLST
Arbitration Lost Interrupt Disable
9
1
write-only
ENDRX
End of Receive Buffer Interrupt Disable
12
1
write-only
ENDTX
End of Transmit Buffer Interrupt Disable
13
1
write-only
EOSACC
End Of Slave Access Interrupt Disable
11
1
write-only
GACC
General Call Access Interrupt Disable
5
1
write-only
NACK
Not Acknowledge Interrupt Disable
8
1
write-only
OVRE
Overrun Error Interrupt Disable
6
1
write-only
RXBUFF
Receive Buffer Full Interrupt Disable
14
1
write-only
RXRDY
Receive Holding Register Ready Interrupt Disable
1
1
write-only
SCL_WS
Clock Wait State Interrupt Disable
10
1
write-only
SVACC
Slave Access Interrupt Disable
4
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Disable
15
1
write-only
TXCOMP
Transmission Completed Interrupt Disable
0
1
write-only
TXRDY
Transmit Holding Register Ready Interrupt Disable
2
1
write-only
IER
Interrupt Enable Register
0x24
32
write-only
n
0x0
0x0
ARBLST
Arbitration Lost Interrupt Enable
9
1
write-only
ENDRX
End of Receive Buffer Interrupt Enable
12
1
write-only
ENDTX
End of Transmit Buffer Interrupt Enable
13
1
write-only
EOSACC
End Of Slave Access Interrupt Enable
11
1
write-only
GACC
General Call Access Interrupt Enable
5
1
write-only
NACK
Not Acknowledge Interrupt Enable
8
1
write-only
OVRE
Overrun Error Interrupt Enable
6
1
write-only
RXBUFF
Receive Buffer Full Interrupt Enable
14
1
write-only
RXRDY
Receive Holding Register Ready Interrupt Enable
1
1
write-only
SCL_WS
Clock Wait State Interrupt Enable
10
1
write-only
SVACC
Slave Access Interrupt Enable
4
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Enable
15
1
write-only
TXCOMP
Transmission Completed Interrupt Enable
0
1
write-only
TXRDY
Transmit Holding Register Ready Interrupt Enable
2
1
write-only
IMR
Interrupt Mask Register
0x2C
32
read-only
n
0x0
0x0
ARBLST
Arbitration Lost Interrupt Mask
9
1
read-only
ENDRX
End of Receive Buffer Interrupt Mask
12
1
read-only
ENDTX
End of Transmit Buffer Interrupt Mask
13
1
read-only
EOSACC
End Of Slave Access Interrupt Mask
11
1
read-only
GACC
General Call Access Interrupt Mask
5
1
read-only
NACK
Not Acknowledge Interrupt Mask
8
1
read-only
OVRE
Overrun Error Interrupt Mask
6
1
read-only
RXBUFF
Receive Buffer Full Interrupt Mask
14
1
read-only
RXRDY
Receive Holding Register Ready Interrupt Mask
1
1
read-only
SCL_WS
Clock Wait State Interrupt Mask
10
1
read-only
SVACC
Slave Access Interrupt Mask
4
1
read-only
TXBUFE
Transmit Buffer Empty Interrupt Mask
15
1
read-only
TXCOMP
Transmission Completed Interrupt Mask
0
1
read-only
TXRDY
Transmit Holding Register Ready Interrupt Mask
2
1
read-only
MMR
Master Mode Register
0x4
32
read-write
n
0x0
0x0
DADR
Device Address
16
7
read-write
IADRSZ
Internal Device Address Size
8
2
read-write
NONE
No internal device address
0x0
1_BYTE
One-byte internal device address
0x1
2_BYTE
Two-byte internal device address
0x2
3_BYTE
Three-byte internal device address
0x3
MREAD
Master Read Direction
12
1
read-write
RHR
Receive Holding Register
0x30
32
read-only
n
0x0
0x0
RXDATA
Master or Slave Receive Holding Data
0
8
read-only
SMR
Slave Mode Register
0x8
32
read-write
n
0x0
0x0
SADR
Slave Address
16
7
read-write
SR
Status Register
0x20
32
read-only
n
0x0
0x0
ARBLST
Arbitration Lost (clear on read)
9
1
read-only
ENDRX
End of RX buffer
12
1
read-only
ENDTX
End of TX buffer
13
1
read-only
EOSACC
End Of Slave Access (clear on read)
11
1
read-only
GACC
General Call Access (clear on read)
5
1
read-only
NACK
Not Acknowledged (clear on read)
8
1
read-only
OVRE
Overrun Error (clear on read)
6
1
read-only
RXBUFF
RX Buffer Full
14
1
read-only
RXRDY
Receive Holding Register Ready (automatically set / reset)
1
1
read-only
SCLWS
Clock Wait State (automatically set / reset)
10
1
read-only
SVACC
Slave Access (automatically set / reset)
4
1
read-only
SVREAD
Slave Read (automatically set / reset)
3
1
read-only
TXBUFE
TX Buffer Empty
15
1
read-only
TXCOMP
Transmission Completed (automatically set / reset)
0
1
read-only
TXRDY
Transmit Holding Register Ready (automatically set / reset)
2
1
read-only
THR
Transmit Holding Register
0x34
32
write-only
n
0x0
0x0
TXDATA
Master or Slave Transmit Holding Data
0
8
write-only
WPMR
Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protection Enable
0
1
read-write
WPKEY
Write Protection Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0
0x545749
WPSR
Write Protection Status Register
0xE8
32
read-only
n
0x0
0x0
WPVS
Write Protection Violation Status
0
1
read-only
WPVSRC
Write Protection Violation Source
8
24
read-only
UART0
Universal Asynchronous Receiver Transmitter 0
UART
0x0
0x0
0x140
registers
n
UART0
8
BRGR
Baud Rate Generator Register
0x20
32
read-write
n
0x0
0x0
CD
Clock Divisor
0
16
read-write
CR
Control Register
0x0
32
write-only
n
0x0
0x0
RSTRX
Reset Receiver
2
1
write-only
RSTSTA
Reset Status
8
1
write-only
RSTTX
Reset Transmitter
3
1
write-only
RXDIS
Receiver Disable
5
1
write-only
RXEN
Receiver Enable
4
1
write-only
TXDIS
Transmitter Disable
7
1
write-only
TXEN
Transmitter Enable
6
1
write-only
IDR
Interrupt Disable Register
0xC
32
write-only
n
0x0
0x0
ENDRX
Disable End of Receive Transfer Interrupt
3
1
write-only
ENDTX
Disable End of Transmit Interrupt
4
1
write-only
FRAME
Disable Framing Error Interrupt
6
1
write-only
OVRE
Disable Overrun Error Interrupt
5
1
write-only
PARE
Disable Parity Error Interrupt
7
1
write-only
RXBUFF
Disable Buffer Full Interrupt
12
1
write-only
RXRDY
Disable RXRDY Interrupt
0
1
write-only
TXBUFE
Disable Buffer Empty Interrupt
11
1
write-only
TXEMPTY
Disable TXEMPTY Interrupt
9
1
write-only
TXRDY
Disable TXRDY Interrupt
1
1
write-only
IER
Interrupt Enable Register
0x8
32
write-only
n
0x0
0x0
ENDRX
Enable End of Receive Transfer Interrupt
3
1
write-only
ENDTX
Enable End of Transmit Interrupt
4
1
write-only
FRAME
Enable Framing Error Interrupt
6
1
write-only
OVRE
Enable Overrun Error Interrupt
5
1
write-only
PARE
Enable Parity Error Interrupt
7
1
write-only
RXBUFF
Enable Buffer Full Interrupt
12
1
write-only
RXRDY
Enable RXRDY Interrupt
0
1
write-only
TXBUFE
Enable Buffer Empty Interrupt
11
1
write-only
TXEMPTY
Enable TXEMPTY Interrupt
9
1
write-only
TXRDY
Enable TXRDY Interrupt
1
1
write-only
IMR
Interrupt Mask Register
0x10
32
read-only
n
0x0
0x0
ENDRX
Mask End of Receive Transfer Interrupt
3
1
read-only
ENDTX
Mask End of Transmit Interrupt
4
1
read-only
FRAME
Mask Framing Error Interrupt
6
1
read-only
OVRE
Mask Overrun Error Interrupt
5
1
read-only
PARE
Mask Parity Error Interrupt
7
1
read-only
RXBUFF
Mask RXBUFF Interrupt
12
1
read-only
RXRDY
Mask RXRDY Interrupt
0
1
read-only
TXBUFE
Mask TXBUFE Interrupt
11
1
read-only
TXEMPTY
Mask TXEMPTY Interrupt
9
1
read-only
TXRDY
Disable TXRDY Interrupt
1
1
read-only
MR
Mode Register
0x4
32
read-write
n
0x0
0x0
CHMODE
Channel Mode
14
2
read-write
NORMAL
Normal mode
0x0
AUTOMATIC
Automatic echo
0x1
LOCAL_LOOPBACK
Local loopback
0x2
REMOTE_LOOPBACK
Remote loopback
0x3
FILTER
Receiver Digital Filter
4
1
read-write
DISABLED
UART does not filter the receive line.
0
ENABLED
UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority).
1
OPT_CLKDIV
Optical Link Clock Divider
16
5
read-write
OPT_CMPTH
Receive Path Comparator Threshold
28
3
read-write
VDDIO_DIV2
Comparator threshold is VDDIO/2 volts.
0x0
VDDIO_DIV2P5
Comparator threshold is VDDIO/2.5 volts.
0x1
VDDIO_DIV3P3
Comparator threshold is VDDIO/3.3 volts.
0x2
VDDIO_DIV5
Comparator threshold is VDDIO/5 volts.
0x3
VDDIO_DIV10
Comparator threshold is VDDIO/10 volts.
0x4
OPT_DUTY
Optical Link Modulation Clock Duty Cycle
24
3
read-write
DUTY_50
Modulation clock duty cycle Is 50%.
0x0
DUTY_43P75
Modulation clock duty cycle Is 43.75%.
0x1
DUTY_37P5
Modulation clock duty cycle Is 37.5%.
0x2
DUTY_31P25
Modulation clock duty cycle Is 31.75%.
0x3
DUTY_25
Modulation clock duty cycle Is 25%.
0x4
DUTY_18P75
Modulation clock duty cycle Is 18.75%.
0x5
DUTY_12P5
Modulation clock duty cycle Is 12.5%.
0x6
DUTY_6P25
Modulation clock duty cycle Is 6.25%.
0x7
OPT_EN
UART Optical Interface Enable
0
1
read-write
DISABLED
The UART transmitter data is not inverted before modulation.
0
ENABLED
The UART transmitter data is inverted before modulation.
1
OPT_MDINV
UART Modulated Data Inverted
2
1
read-write
DISABLED
The output of the modulator is not inverted.
0
ENABLED
The output of the modulator is inverted.
1
OPT_RXINV
UART Receive Data Inverted
1
1
read-write
DISABLED
The comparator data output is not inverted before entering UART.
0
ENABLED
The comparator data output is inverted before entering UART.
1
PAR
Parity Type
9
3
read-write
EVEN
Even Parity
0x0
ODD
Odd Parity
0x1
SPACE
Space: parity forced to 0
0x2
MARK
Mark: parity forced to 1
0x3
NO
No parity
0x4
PTCR
Transfer Control Register
0x120
32
write-only
n
0x0
0x0
RXTDIS
Receiver Transfer Disable
1
1
write-only
RXTEN
Receiver Transfer Enable
0
1
write-only
TXTDIS
Transmitter Transfer Disable
9
1
write-only
TXTEN
Transmitter Transfer Enable
8
1
write-only
PTSR
Transfer Status Register
0x124
32
read-only
n
0x0
0x0
RXTEN
Receiver Transfer Enable
0
1
read-only
TXTEN
Transmitter Transfer Enable
8
1
read-only
RCR
Receive Counter Register
0x104
32
read-write
n
0x0
0x0
RXCTR
Receive Counter Register
0
16
read-write
RHR
Receive Holding Register
0x18
32
read-only
n
0x0
0x0
RXCHR
Received Character
0
8
read-only
RNCR
Receive Next Counter Register
0x114
32
read-write
n
0x0
0x0
RXNCTR
Receive Next Counter
0
16
read-write
RNPR
Receive Next Pointer Register
0x110
32
read-write
n
0x0
0x0
RXNPTR
Receive Next Pointer
0
32
read-write
RPR
Receive Pointer Register
0x100
32
read-write
n
0x0
0x0
RXPTR
Receive Pointer Register
0
32
read-write
SR
Status Register
0x14
32
read-only
n
0x0
0x0
ENDRX
End of Receiver Transfer
3
1
read-only
ENDTX
End of Transmitter Transfer
4
1
read-only
FRAME
Framing Error
6
1
read-only
OVRE
Overrun Error
5
1
read-only
PARE
Parity Error
7
1
read-only
RXBUFF
Receive Buffer Full
12
1
read-only
RXRDY
Receiver Ready
0
1
read-only
TXBUFE
Transmission Buffer Empty
11
1
read-only
TXEMPTY
Transmitter Empty
9
1
read-only
TXRDY
Transmitter Ready
1
1
read-only
TCR
Transmit Counter Register
0x10C
32
read-write
n
0x0
0x0
TXCTR
Transmit Counter Register
0
16
read-write
THR
Transmit Holding Register
0x1C
32
write-only
n
0x0
0x0
TXCHR
Character to be Transmitted
0
8
write-only
TNCR
Transmit Next Counter Register
0x11C
32
read-write
n
0x0
0x0
TXNCTR
Transmit Counter Next
0
16
read-write
TNPR
Transmit Next Pointer Register
0x118
32
read-write
n
0x0
0x0
TXNPTR
Transmit Next Pointer
0
32
read-write
TPR
Transmit Pointer Register
0x108
32
read-write
n
0x0
0x0
TXPTR
Transmit Counter Register
0
32
read-write
UART1
Universal Asynchronous Receiver Transmitter 1
UART
0x0
0x0
0x50
registers
n
UART1
38
BRGR
Baud Rate Generator Register
0x20
32
read-write
n
0x0
0x0
CD
Clock Divisor
0
16
read-write
CR
Control Register
0x0
32
write-only
n
0x0
0x0
RSTRX
Reset Receiver
2
1
write-only
RSTSTA
Reset Status
8
1
write-only
RSTTX
Reset Transmitter
3
1
write-only
RXDIS
Receiver Disable
5
1
write-only
RXEN
Receiver Enable
4
1
write-only
TXDIS
Transmitter Disable
7
1
write-only
TXEN
Transmitter Enable
6
1
write-only
IDR
Interrupt Disable Register
0xC
32
write-only
n
0x0
0x0
ENDRX
Disable End of Receive Transfer Interrupt
3
1
write-only
ENDTX
Disable End of Transmit Interrupt
4
1
write-only
FRAME
Disable Framing Error Interrupt
6
1
write-only
OVRE
Disable Overrun Error Interrupt
5
1
write-only
PARE
Disable Parity Error Interrupt
7
1
write-only
RXBUFF
Disable Buffer Full Interrupt
12
1
write-only
RXRDY
Disable RXRDY Interrupt
0
1
write-only
TXBUFE
Disable Buffer Empty Interrupt
11
1
write-only
TXEMPTY
Disable TXEMPTY Interrupt
9
1
write-only
TXRDY
Disable TXRDY Interrupt
1
1
write-only
IER
Interrupt Enable Register
0x8
32
write-only
n
0x0
0x0
ENDRX
Enable End of Receive Transfer Interrupt
3
1
write-only
ENDTX
Enable End of Transmit Interrupt
4
1
write-only
FRAME
Enable Framing Error Interrupt
6
1
write-only
OVRE
Enable Overrun Error Interrupt
5
1
write-only
PARE
Enable Parity Error Interrupt
7
1
write-only
RXBUFF
Enable Buffer Full Interrupt
12
1
write-only
RXRDY
Enable RXRDY Interrupt
0
1
write-only
TXBUFE
Enable Buffer Empty Interrupt
11
1
write-only
TXEMPTY
Enable TXEMPTY Interrupt
9
1
write-only
TXRDY
Enable TXRDY Interrupt
1
1
write-only
IMR
Interrupt Mask Register
0x10
32
read-only
n
0x0
0x0
ENDRX
Mask End of Receive Transfer Interrupt
3
1
read-only
ENDTX
Mask End of Transmit Interrupt
4
1
read-only
FRAME
Mask Framing Error Interrupt
6
1
read-only
OVRE
Mask Overrun Error Interrupt
5
1
read-only
PARE
Mask Parity Error Interrupt
7
1
read-only
RXBUFF
Mask RXBUFF Interrupt
12
1
read-only
RXRDY
Mask RXRDY Interrupt
0
1
read-only
TXBUFE
Mask TXBUFE Interrupt
11
1
read-only
TXEMPTY
Mask TXEMPTY Interrupt
9
1
read-only
TXRDY
Disable TXRDY Interrupt
1
1
read-only
MR
Mode Register
0x4
32
read-write
n
0x0
0x0
CHMODE
Channel Mode
14
2
read-write
NORMAL
Normal mode
0x0
AUTOMATIC
Automatic echo
0x1
LOCAL_LOOPBACK
Local loopback
0x2
REMOTE_LOOPBACK
Remote loopback
0x3
FILTER
Receiver Digital Filter
4
1
read-write
DISABLED
UART does not filter the receive line.
0
ENABLED
UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority).
1
OPT_CLKDIV
Optical Link Clock Divider
16
5
read-write
OPT_CMPTH
Receive Path Comparator Threshold
28
3
read-write
VDDIO_DIV2
Comparator threshold is VDDIO/2 volts.
0x0
VDDIO_DIV2P5
Comparator threshold is VDDIO/2.5 volts.
0x1
VDDIO_DIV3P3
Comparator threshold is VDDIO/3.3 volts.
0x2
VDDIO_DIV5
Comparator threshold is VDDIO/5 volts.
0x3
VDDIO_DIV10
Comparator threshold is VDDIO/10 volts.
0x4
OPT_DUTY
Optical Link Modulation Clock Duty Cycle
24
3
read-write
DUTY_50
Modulation clock duty cycle Is 50%.
0x0
DUTY_43P75
Modulation clock duty cycle Is 43.75%.
0x1
DUTY_37P5
Modulation clock duty cycle Is 37.5%.
0x2
DUTY_31P25
Modulation clock duty cycle Is 31.75%.
0x3
DUTY_25
Modulation clock duty cycle Is 25%.
0x4
DUTY_18P75
Modulation clock duty cycle Is 18.75%.
0x5
DUTY_12P5
Modulation clock duty cycle Is 12.5%.
0x6
DUTY_6P25
Modulation clock duty cycle Is 6.25%.
0x7
OPT_EN
UART Optical Interface Enable
0
1
read-write
DISABLED
The UART transmitter data is not inverted before modulation.
0
ENABLED
The UART transmitter data is inverted before modulation.
1
OPT_MDINV
UART Modulated Data Inverted
2
1
read-write
DISABLED
The output of the modulator is not inverted.
0
ENABLED
The output of the modulator is inverted.
1
OPT_RXINV
UART Receive Data Inverted
1
1
read-write
DISABLED
The comparator data output is not inverted before entering UART.
0
ENABLED
The comparator data output is inverted before entering UART.
1
PAR
Parity Type
9
3
read-write
EVEN
Even Parity
0x0
ODD
Odd Parity
0x1
SPACE
Space: parity forced to 0
0x2
MARK
Mark: parity forced to 1
0x3
NO
No parity
0x4
PTCR
Transfer Control Register
0x120
32
write-only
n
0x0
0x0
RXTDIS
Receiver Transfer Disable
1
1
write-only
RXTEN
Receiver Transfer Enable
0
1
write-only
TXTDIS
Transmitter Transfer Disable
9
1
write-only
TXTEN
Transmitter Transfer Enable
8
1
write-only
PTSR
Transfer Status Register
0x124
32
read-only
n
0x0
0x0
RXTEN
Receiver Transfer Enable
0
1
read-only
TXTEN
Transmitter Transfer Enable
8
1
read-only
RCR
Receive Counter Register
0x104
32
read-write
n
0x0
0x0
RXCTR
Receive Counter Register
0
16
read-write
RHR
Receive Holding Register
0x18
32
read-only
n
0x0
0x0
RXCHR
Received Character
0
8
read-only
RNCR
Receive Next Counter Register
0x114
32
read-write
n
0x0
0x0
RXNCTR
Receive Next Counter
0
16
read-write
RNPR
Receive Next Pointer Register
0x110
32
read-write
n
0x0
0x0
RXNPTR
Receive Next Pointer
0
32
read-write
RPR
Receive Pointer Register
0x100
32
read-write
n
0x0
0x0
RXPTR
Receive Pointer Register
0
32
read-write
SR
Status Register
0x14
32
read-only
n
0x0
0x0
ENDRX
End of Receiver Transfer
3
1
read-only
ENDTX
End of Transmitter Transfer
4
1
read-only
FRAME
Framing Error
6
1
read-only
OVRE
Overrun Error
5
1
read-only
PARE
Parity Error
7
1
read-only
RXBUFF
Receive Buffer Full
12
1
read-only
RXRDY
Receiver Ready
0
1
read-only
TXBUFE
Transmission Buffer Empty
11
1
read-only
TXEMPTY
Transmitter Empty
9
1
read-only
TXRDY
Transmitter Ready
1
1
read-only
TCR
Transmit Counter Register
0x10C
32
read-write
n
0x0
0x0
TXCTR
Transmit Counter Register
0
16
read-write
THR
Transmit Holding Register
0x1C
32
write-only
n
0x0
0x0
TXCHR
Character to be Transmitted
0
8
write-only
TNCR
Transmit Next Counter Register
0x11C
32
read-write
n
0x0
0x0
TXNCTR
Transmit Counter Next
0
16
read-write
TNPR
Transmit Next Pointer Register
0x118
32
read-write
n
0x0
0x0
TXNPTR
Transmit Next Pointer
0
32
read-write
TPR
Transmit Pointer Register
0x108
32
read-write
n
0x0
0x0
TXPTR
Transmit Counter Register
0
32
read-write
USART0
Universal Synchronous Asynchronous Receiver Transmitter 0
USART
0x0
0x0
0x50
registers
n
USART0
14
BRGR
Baud Rate Generator Register
0x20
32
read-write
n
0x0
0x0
CD
Clock Divider
0
16
read-write
FP
Fractional Part
16
3
read-write
CR
Control Register
0x0
32
write-only
n
0x0
0x0
RETTO
Rearm Time-out
15
1
write-only
RSTIT
Reset Iterations
13
1
write-only
RSTNACK
Reset Non Acknowledge
14
1
write-only
RSTRX
Reset Receiver
2
1
write-only
RSTSTA
Reset Status Bits
8
1
write-only
RSTTX
Reset Transmitter
3
1
write-only
RTSDIS
Request to Send Disable
19
1
write-only
RTSEN
Request to Send Enable
18
1
write-only
RXDIS
Receiver Disable
5
1
write-only
RXEN
Receiver Enable
4
1
write-only
SENDA
Send Address
12
1
write-only
STPBRK
Stop Break
10
1
write-only
STTBRK
Start Break
9
1
write-only
STTTO
Start Time-out
11
1
write-only
TXDIS
Transmitter Disable
7
1
write-only
TXEN
Transmitter Enable
6
1
write-only
CR_SPI_MODE
Control Register
SPI_MODE
0x0
32
write-only
n
0x0
0x0
FCS
Force SPI Chip Select
18
1
write-only
RCS
Release SPI Chip Select
19
1
write-only
RSTRX
Reset Receiver
2
1
write-only
RSTSTA
Reset Status Bits
8
1
write-only
RSTTX
Reset Transmitter
3
1
write-only
RXDIS
Receiver Disable
5
1
write-only
RXEN
Receiver Enable
4
1
write-only
TXDIS
Transmitter Disable
7
1
write-only
TXEN
Transmitter Enable
6
1
write-only
CSR
Channel Status Register
0x14
32
read-only
n
0x0
0x0
CTS
Image of CTS Input
23
1
read-only
CTSIC
Clear to Send Input Change Flag (clear on read)
19
1
read-only
ENDRX
End of RX Buffer
3
1
read-only
ENDTX
End of TX Buffer
4
1
read-only
FRAME
Framing Error
6
1
read-only
ITER
Max Number of Repetitions Reached
10
1
read-only
MANERR
Manchester Error
24
1
read-only
NACK
Non Acknowledge Interrupt
13
1
read-only
OVRE
Overrun Error
5
1
read-only
PARE
Parity Error
7
1
read-only
RXBRK
Break Received/End of Break
2
1
read-only
RXBUFF
RX Buffer Full
12
1
read-only
RXRDY
Receiver Ready (automatically set / reset)
0
1
read-only
TIMEOUT
Receiver Time-out
8
1
read-only
TXBUFE
TX Buffer Empty
11
1
read-only
TXEMPTY
Transmitter Empty (automatically set / reset)
9
1
read-only
TXRDY
Transmitter Ready (automatically set / reset)
1
1
read-only
CSR_SPI_MODE
Channel Status Register
SPI_MODE
0x14
32
read-only
n
0x0
0x0
ENDRX
3
1
read-only
ENDTX
4
1
read-only
OVRE
Overrun Error
5
1
read-only
RXBUFF
12
1
read-only
RXRDY
Receiver Ready (automatically set / reset)
0
1
read-only
TXBUFE
11
1
read-only
TXEMPTY
Transmitter Empty (automatically set / reset)
9
1
read-only
TXRDY
Transmitter Ready (automatically set / reset)
1
1
read-only
UNRE
Underrun Error
10
1
read-only
FIDI
FI DI Ratio Register
0x40
32
read-write
n
0x0
0x0
FI_DI_RATIO
FI Over DI Ratio Value
0
11
read-write
IDR
Interrupt Disable Register
0xC
32
write-only
n
0x0
0x0
CTSIC
Clear to Send Input Change Interrupt Disable
19
1
write-only
ENDRX
End of Receive Buffer Transfer Interrupt Disable (available in all USART modes of operation)
3
1
write-only
ENDTX
End of Transmit Buffer Interrupt Disable (available in all USART modes of operation)
4
1
write-only
FRAME
Framing Error Interrupt Disable
6
1
write-only
ITER
Max Number of Repetitions Reached Interrupt Disable
10
1
write-only
MANE
Manchester Error Interrupt Disable
24
1
write-only
NACK
Non Acknowledge Interrupt Disable
13
1
write-only
OVRE
Overrun Error Interrupt Enable
5
1
write-only
PARE
Parity Error Interrupt Disable
7
1
write-only
RXBRK
Receiver Break Interrupt Disable
2
1
write-only
RXBUFF
Receive Buffer Full Interrupt Disable (available in all USART modes of operation)
12
1
write-only
RXRDY
RXRDY Interrupt Disable
0
1
write-only
TIMEOUT
Time-out Interrupt Disable
8
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Disable (available in all USART modes of operation)
11
1
write-only
TXEMPTY
TXEMPTY Interrupt Disable
9
1
write-only
TXRDY
TXRDY Interrupt Disable
1
1
write-only
IDR_SPI_MODE
Interrupt Disable Register
SPI_MODE
0xC
32
write-only
n
0x0
0x0
ENDRX
3
1
write-only
ENDTX
4
1
write-only
OVRE
Overrun Error Interrupt Disable
5
1
write-only
RXBUFF
12
1
write-only
RXRDY
RXRDY Interrupt Disable
0
1
write-only
TXBUFE
11
1
write-only
TXEMPTY
TXEMPTY Interrupt Disable
9
1
write-only
TXRDY
TXRDY Interrupt Disable
1
1
write-only
UNRE
SPI Underrun Error Interrupt Disable
10
1
write-only
IER
Interrupt Enable Register
0x8
32
write-only
n
0x0
0x0
CTSIC
Clear to Send Input Change Interrupt Enable
19
1
write-only
ENDRX
End of Receive Buffer Interrupt Enable (available in all USART modes of operation)
3
1
write-only
ENDTX
End of Transmit Buffer Interrupt Enable (available in all USART modes of operation)
4
1
write-only
FRAME
Framing Error Interrupt Enable
6
1
write-only
ITER
Max number of Repetitions Reached Interrupt Enable
10
1
write-only
MANE
Manchester Error Interrupt Enable
24
1
write-only
NACK
Non Acknowledge Interrupt Enable
13
1
write-only
OVRE
Overrun Error Interrupt Enable
5
1
write-only
PARE
Parity Error Interrupt Enable
7
1
write-only
RXBRK
Receiver Break Interrupt Enable
2
1
write-only
RXBUFF
Receive Buffer Full Interrupt Enable (available in all USART modes of operation)
12
1
write-only
RXRDY
RXRDY Interrupt Enable
0
1
write-only
TIMEOUT
Time-out Interrupt Enable
8
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation)
11
1
write-only
TXEMPTY
TXEMPTY Interrupt Enable
9
1
write-only
TXRDY
TXRDY Interrupt Enable
1
1
write-only
IER_SPI_MODE
Interrupt Enable Register
SPI_MODE
0x8
32
write-only
n
0x0
0x0
ENDRX
3
1
write-only
ENDTX
4
1
write-only
OVRE
Overrun Error Interrupt Enable
5
1
write-only
RXBUFF
12
1
write-only
RXRDY
RXRDY Interrupt Enable
0
1
write-only
TXBUFE
11
1
write-only
TXEMPTY
TXEMPTY Interrupt Enable
9
1
write-only
TXRDY
TXRDY Interrupt Enable
1
1
write-only
UNRE
SPI Underrun Error Interrupt Enable
10
1
write-only
IF
IrDA Filter Register
0x4C
32
read-write
n
0x0
0x0
IRDA_FILTER
IrDA Filter
0
8
read-write
IMR
Interrupt Mask Register
0x10
32
read-only
n
0x0
0x0
CTSIC
Clear to Send Input Change Interrupt Mask
19
1
read-only
ENDRX
End of Receive Buffer Interrupt Mask (available in all USART modes of operation)
3
1
read-only
ENDTX
End of Transmit Buffer Interrupt Mask (available in all USART modes of operation)
4
1
read-only
FRAME
Framing Error Interrupt Mask
6
1
read-only
ITER
Max Number of Repetitions Reached Interrupt Mask
10
1
read-only
MANE
Manchester Error Interrupt Mask
24
1
read-only
NACK
Non Acknowledge Interrupt Mask
13
1
read-only
OVRE
Overrun Error Interrupt Mask
5
1
read-only
PARE
Parity Error Interrupt Mask
7
1
read-only
RXBRK
Receiver Break Interrupt Mask
2
1
read-only
RXBUFF
Receive Buffer Full Interrupt Mask (available in all USART modes of operation)
12
1
read-only
RXRDY
RXRDY Interrupt Mask
0
1
read-only
TIMEOUT
Time-out Interrupt Mask
8
1
read-only
TXBUFE
Transmit Buffer Empty Interrupt Mask (available in all USART modes of operation)
11
1
read-only
TXEMPTY
TXEMPTY Interrupt Mask
9
1
read-only
TXRDY
TXRDY Interrupt Mask
1
1
read-only
IMR_SPI_MODE
Interrupt Mask Register
SPI_MODE
0x10
32
read-only
n
0x0
0x0
ENDRX
3
1
read-only
ENDTX
4
1
read-only
OVRE
Overrun Error Interrupt Mask
5
1
read-only
RXBUFF
12
1
read-only
RXRDY
RXRDY Interrupt Mask
0
1
read-only
TXBUFE
11
1
read-only
TXEMPTY
TXEMPTY Interrupt Mask
9
1
read-only
TXRDY
TXRDY Interrupt Mask
1
1
read-only
UNRE
SPI Underrun Error Interrupt Mask
10
1
read-only
MAN
Manchester Configuration Register
0x50
32
read-write
n
0x0
0x0
DRIFT
Drift Compensation
30
1
read-write
ONE
Must Be Set to 1
29
1
read-write
RX_MPOL
Receiver Manchester Polarity
28
1
read-write
RX_PL
Receiver Preamble Length
16
4
read-write
RX_PP
Receiver Preamble Pattern detected
24
2
read-write
ALL_ONE
The preamble is composed of '1's
0x0
ALL_ZERO
The preamble is composed of '0's
0x1
ZERO_ONE
The preamble is composed of '01's
0x2
ONE_ZERO
The preamble is composed of '10's
0x3
TX_MPOL
Transmitter Manchester Polarity
12
1
read-write
TX_PL
Transmitter Preamble Length
0
4
read-write
TX_PP
Transmitter Preamble Pattern
8
2
read-write
ALL_ONE
The preamble is composed of '1's
0x0
ALL_ZERO
The preamble is composed of '0's
0x1
ZERO_ONE
The preamble is composed of '01's
0x2
ONE_ZERO
The preamble is composed of '10's
0x3
MR
Mode Register
0x4
32
read-write
n
0x0
0x0
CHMODE
Channel Mode
14
2
read-write
NORMAL
Normal mode
0x0
AUTOMATIC
Automatic Echo. Receiver input is connected to the TXD pin.
0x1
LOCAL_LOOPBACK
Local Loopback. Transmitter output is connected to the Receiver Input.
0x2
REMOTE_LOOPBACK
Remote Loopback. RXD pin is internally connected to the TXD pin.
0x3
CHRL
Character Length
6
2
read-write
5_BIT
Character length is 5 bits
0x0
6_BIT
Character length is 6 bits
0x1
7_BIT
Character length is 7 bits
0x2
8_BIT
Character length is 8 bits
0x3
CLKO
Clock Output Select
18
1
read-write
DSNACK
Disable Successive NACK
21
1
read-write
FILTER
Receive Line Filter
28
1
read-write
INACK
Inhibit Non Acknowledge
20
1
read-write
INVDATA
Inverted Data
23
1
read-write
MAN
Manchester Encoder/Decoder Enable
29
1
read-write
MAX_ITERATION
Maximum Number of Automatic Iteration
24
3
read-write
MODE9
9-bit Character Length
17
1
read-write
MODSYNC
Manchester Synchronization Mode
30
1
read-write
MSBF
Bit Order
16
1
read-write
NBSTOP
Number of Stop Bits
12
2
read-write
1_BIT
1 stop bit
0x0
1_5_BIT
1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
0x1
2_BIT
2 stop bits
0x2
ONEBIT
Start Frame Delimiter Selector
31
1
read-write
OVER
Oversampling Mode
19
1
read-write
PAR
Parity Type
9
3
read-write
EVEN
Even parity
0x0
ODD
Odd parity
0x1
SPACE
Parity forced to 0 (Space)
0x2
MARK
Parity forced to 1 (Mark)
0x3
NO
No parity
0x4
MULTIDROP
Multidrop mode
0x6
SYNC
Synchronous Mode Select
8
1
read-write
USART_MODE
USART Mode of Operation
0
4
read-write
NORMAL
Normal mode
0x0
RS485
RS485
0x1
HW_HANDSHAKING
Hardware Handshaking
0x2
IS07816_T_0
IS07816 Protocol: T = 0
0x4
IS07816_T_1
IS07816 Protocol: T = 1
0x6
IRDA
IrDA
0x8
SPI_MASTER
SPI master
0xE
SPI_SLAVE
SPI Slave
0xF
USCLKS
Clock Selection
4
2
read-write
MCK
Peripheral clock is selected
0x0
DIV
Peripheral clock divided (DIV=8) is selected
0x1
SCK
Serial clock (SCK) is selected
0x3
VAR_SYNC
Variable Synchronization of Command/Data Sync Start Frame Delimiter
22
1
read-write
MR_SPI_MODE
Mode Register
SPI_MODE
0x4
32
read-write
n
0x0
0x0
CHRL
Character Length
6
2
read-write
8_BIT
Character length is 8 bits
0x3
CLKO
Clock Output Select
18
1
read-write
CPHA
SPI Clock Phase
8
1
read-write
CPOL
SPI Clock Polarity
16
1
read-write
USART_MODE
USART Mode of Operation
0
4
read-write
SPI_MASTER
SPI master
0xE
SPI_SLAVE
SPI Slave
0xF
USCLKS
Clock Selection
4
2
read-write
MCK
Peripheral clock is selected
0x0
DIV
Peripheral clock divided (DIV=8) is selected
0x1
SCK
Serial Clock SLK is selected
0x3
WRDBT
Wait Read Data Before Transfer
20
1
read-write
NER
Number of Errors Register
0x44
32
read-only
n
0x0
0x0
NB_ERRORS
Number of Errors
0
8
read-only
PTCR
Transfer Control Register
0x120
32
write-only
n
0x0
0x0
RXTDIS
Receiver Transfer Disable
1
1
write-only
RXTEN
Receiver Transfer Enable
0
1
write-only
TXTDIS
Transmitter Transfer Disable
9
1
write-only
TXTEN
Transmitter Transfer Enable
8
1
write-only
PTSR
Transfer Status Register
0x124
32
read-only
n
0x0
0x0
RXTEN
Receiver Transfer Enable
0
1
read-only
TXTEN
Transmitter Transfer Enable
8
1
read-only
RCR
Receive Counter Register
0x104
32
read-write
n
0x0
0x0
RXCTR
Receive Counter Register
0
16
read-write
RHR
Receive Holding Register
0x18
32
read-only
n
0x0
0x0
RXCHR
Received Character
0
9
read-only
RXSYNH
Received Sync
15
1
read-only
RNCR
Receive Next Counter Register
0x114
32
read-write
n
0x0
0x0
RXNCTR
Receive Next Counter
0
16
read-write
RNPR
Receive Next Pointer Register
0x110
32
read-write
n
0x0
0x0
RXNPTR
Receive Next Pointer
0
32
read-write
RPR
Receive Pointer Register
0x100
32
read-write
n
0x0
0x0
RXPTR
Receive Pointer Register
0
32
read-write
RTOR
Receiver Time-out Register
0x24
32
read-write
n
0x0
0x0
TO
Time-out Value
0
16
read-write
TCR
Transmit Counter Register
0x10C
32
read-write
n
0x0
0x0
TXCTR
Transmit Counter Register
0
16
read-write
THR
Transmit Holding Register
0x1C
32
write-only
n
0x0
0x0
TXCHR
Character to be Transmitted
0
9
write-only
TXSYNH
Sync Field to be Transmitted
15
1
write-only
TNCR
Transmit Next Counter Register
0x11C
32
read-write
n
0x0
0x0
TXNCTR
Transmit Counter Next
0
16
read-write
TNPR
Transmit Next Pointer Register
0x118
32
read-write
n
0x0
0x0
TXNPTR
Transmit Next Pointer
0
32
read-write
TPR
Transmit Pointer Register
0x108
32
read-write
n
0x0
0x0
TXPTR
Transmit Counter Register
0
32
read-write
TTGR
Transmitter Timeguard Register
0x28
32
read-write
n
0x0
0x0
TG
Timeguard Value
0
8
read-write
WPMR
Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protection Enable
0
1
read-write
WPKEY
Write Protection Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
0x555341
WPSR
Write Protection Status Register
0xE8
32
read-only
n
0x0
0x0
WPVS
Write Protection Violation Status
0
1
read-only
WPVSRC
Write Protection Violation Source
8
16
read-only
USART1
Universal Synchronous Asynchronous Receiver Transmitter 1
USART
0x0
0x0
0x50
registers
n
USART1
15
BRGR
Baud Rate Generator Register
0x20
32
read-write
n
0x0
0x0
CD
Clock Divider
0
16
read-write
FP
Fractional Part
16
3
read-write
CR
Control Register
0x0
32
write-only
n
0x0
0x0
RETTO
Rearm Time-out
15
1
write-only
RSTIT
Reset Iterations
13
1
write-only
RSTNACK
Reset Non Acknowledge
14
1
write-only
RSTRX
Reset Receiver
2
1
write-only
RSTSTA
Reset Status Bits
8
1
write-only
RSTTX
Reset Transmitter
3
1
write-only
RTSDIS
Request to Send Disable
19
1
write-only
RTSEN
Request to Send Enable
18
1
write-only
RXDIS
Receiver Disable
5
1
write-only
RXEN
Receiver Enable
4
1
write-only
SENDA
Send Address
12
1
write-only
STPBRK
Stop Break
10
1
write-only
STTBRK
Start Break
9
1
write-only
STTTO
Start Time-out
11
1
write-only
TXDIS
Transmitter Disable
7
1
write-only
TXEN
Transmitter Enable
6
1
write-only
CR_SPI_MODE
Control Register
SPI_MODE
0x0
32
write-only
n
0x0
0x0
FCS
Force SPI Chip Select
18
1
write-only
RCS
Release SPI Chip Select
19
1
write-only
RSTRX
Reset Receiver
2
1
write-only
RSTSTA
Reset Status Bits
8
1
write-only
RSTTX
Reset Transmitter
3
1
write-only
RXDIS
Receiver Disable
5
1
write-only
RXEN
Receiver Enable
4
1
write-only
TXDIS
Transmitter Disable
7
1
write-only
TXEN
Transmitter Enable
6
1
write-only
CSR
Channel Status Register
0x14
32
read-only
n
0x0
0x0
CTS
Image of CTS Input
23
1
read-only
CTSIC
Clear to Send Input Change Flag (clear on read)
19
1
read-only
ENDRX
End of RX Buffer
3
1
read-only
ENDTX
End of TX Buffer
4
1
read-only
FRAME
Framing Error
6
1
read-only
ITER
Max Number of Repetitions Reached
10
1
read-only
MANERR
Manchester Error
24
1
read-only
NACK
Non Acknowledge Interrupt
13
1
read-only
OVRE
Overrun Error
5
1
read-only
PARE
Parity Error
7
1
read-only
RXBRK
Break Received/End of Break
2
1
read-only
RXBUFF
RX Buffer Full
12
1
read-only
RXRDY
Receiver Ready (automatically set / reset)
0
1
read-only
TIMEOUT
Receiver Time-out
8
1
read-only
TXBUFE
TX Buffer Empty
11
1
read-only
TXEMPTY
Transmitter Empty (automatically set / reset)
9
1
read-only
TXRDY
Transmitter Ready (automatically set / reset)
1
1
read-only
CSR_SPI_MODE
Channel Status Register
SPI_MODE
0x14
32
read-only
n
0x0
0x0
ENDRX
3
1
read-only
ENDTX
4
1
read-only
OVRE
Overrun Error
5
1
read-only
RXBUFF
12
1
read-only
RXRDY
Receiver Ready (automatically set / reset)
0
1
read-only
TXBUFE
11
1
read-only
TXEMPTY
Transmitter Empty (automatically set / reset)
9
1
read-only
TXRDY
Transmitter Ready (automatically set / reset)
1
1
read-only
UNRE
Underrun Error
10
1
read-only
FIDI
FI DI Ratio Register
0x40
32
read-write
n
0x0
0x0
FI_DI_RATIO
FI Over DI Ratio Value
0
11
read-write
IDR
Interrupt Disable Register
0xC
32
write-only
n
0x0
0x0
CTSIC
Clear to Send Input Change Interrupt Disable
19
1
write-only
ENDRX
End of Receive Buffer Transfer Interrupt Disable (available in all USART modes of operation)
3
1
write-only
ENDTX
End of Transmit Buffer Interrupt Disable (available in all USART modes of operation)
4
1
write-only
FRAME
Framing Error Interrupt Disable
6
1
write-only
ITER
Max Number of Repetitions Reached Interrupt Disable
10
1
write-only
MANE
Manchester Error Interrupt Disable
24
1
write-only
NACK
Non Acknowledge Interrupt Disable
13
1
write-only
OVRE
Overrun Error Interrupt Enable
5
1
write-only
PARE
Parity Error Interrupt Disable
7
1
write-only
RXBRK
Receiver Break Interrupt Disable
2
1
write-only
RXBUFF
Receive Buffer Full Interrupt Disable (available in all USART modes of operation)
12
1
write-only
RXRDY
RXRDY Interrupt Disable
0
1
write-only
TIMEOUT
Time-out Interrupt Disable
8
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Disable (available in all USART modes of operation)
11
1
write-only
TXEMPTY
TXEMPTY Interrupt Disable
9
1
write-only
TXRDY
TXRDY Interrupt Disable
1
1
write-only
IDR_SPI_MODE
Interrupt Disable Register
SPI_MODE
0xC
32
write-only
n
0x0
0x0
ENDRX
3
1
write-only
ENDTX
4
1
write-only
OVRE
Overrun Error Interrupt Disable
5
1
write-only
RXBUFF
12
1
write-only
RXRDY
RXRDY Interrupt Disable
0
1
write-only
TXBUFE
11
1
write-only
TXEMPTY
TXEMPTY Interrupt Disable
9
1
write-only
TXRDY
TXRDY Interrupt Disable
1
1
write-only
UNRE
SPI Underrun Error Interrupt Disable
10
1
write-only
IER
Interrupt Enable Register
0x8
32
write-only
n
0x0
0x0
CTSIC
Clear to Send Input Change Interrupt Enable
19
1
write-only
ENDRX
End of Receive Buffer Interrupt Enable (available in all USART modes of operation)
3
1
write-only
ENDTX
End of Transmit Buffer Interrupt Enable (available in all USART modes of operation)
4
1
write-only
FRAME
Framing Error Interrupt Enable
6
1
write-only
ITER
Max number of Repetitions Reached Interrupt Enable
10
1
write-only
MANE
Manchester Error Interrupt Enable
24
1
write-only
NACK
Non Acknowledge Interrupt Enable
13
1
write-only
OVRE
Overrun Error Interrupt Enable
5
1
write-only
PARE
Parity Error Interrupt Enable
7
1
write-only
RXBRK
Receiver Break Interrupt Enable
2
1
write-only
RXBUFF
Receive Buffer Full Interrupt Enable (available in all USART modes of operation)
12
1
write-only
RXRDY
RXRDY Interrupt Enable
0
1
write-only
TIMEOUT
Time-out Interrupt Enable
8
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation)
11
1
write-only
TXEMPTY
TXEMPTY Interrupt Enable
9
1
write-only
TXRDY
TXRDY Interrupt Enable
1
1
write-only
IER_SPI_MODE
Interrupt Enable Register
SPI_MODE
0x8
32
write-only
n
0x0
0x0
ENDRX
3
1
write-only
ENDTX
4
1
write-only
OVRE
Overrun Error Interrupt Enable
5
1
write-only
RXBUFF
12
1
write-only
RXRDY
RXRDY Interrupt Enable
0
1
write-only
TXBUFE
11
1
write-only
TXEMPTY
TXEMPTY Interrupt Enable
9
1
write-only
TXRDY
TXRDY Interrupt Enable
1
1
write-only
UNRE
SPI Underrun Error Interrupt Enable
10
1
write-only
IF
IrDA Filter Register
0x4C
32
read-write
n
0x0
0x0
IRDA_FILTER
IrDA Filter
0
8
read-write
IMR
Interrupt Mask Register
0x10
32
read-only
n
0x0
0x0
CTSIC
Clear to Send Input Change Interrupt Mask
19
1
read-only
ENDRX
End of Receive Buffer Interrupt Mask (available in all USART modes of operation)
3
1
read-only
ENDTX
End of Transmit Buffer Interrupt Mask (available in all USART modes of operation)
4
1
read-only
FRAME
Framing Error Interrupt Mask
6
1
read-only
ITER
Max Number of Repetitions Reached Interrupt Mask
10
1
read-only
MANE
Manchester Error Interrupt Mask
24
1
read-only
NACK
Non Acknowledge Interrupt Mask
13
1
read-only
OVRE
Overrun Error Interrupt Mask
5
1
read-only
PARE
Parity Error Interrupt Mask
7
1
read-only
RXBRK
Receiver Break Interrupt Mask
2
1
read-only
RXBUFF
Receive Buffer Full Interrupt Mask (available in all USART modes of operation)
12
1
read-only
RXRDY
RXRDY Interrupt Mask
0
1
read-only
TIMEOUT
Time-out Interrupt Mask
8
1
read-only
TXBUFE
Transmit Buffer Empty Interrupt Mask (available in all USART modes of operation)
11
1
read-only
TXEMPTY
TXEMPTY Interrupt Mask
9
1
read-only
TXRDY
TXRDY Interrupt Mask
1
1
read-only
IMR_SPI_MODE
Interrupt Mask Register
SPI_MODE
0x10
32
read-only
n
0x0
0x0
ENDRX
3
1
read-only
ENDTX
4
1
read-only
OVRE
Overrun Error Interrupt Mask
5
1
read-only
RXBUFF
12
1
read-only
RXRDY
RXRDY Interrupt Mask
0
1
read-only
TXBUFE
11
1
read-only
TXEMPTY
TXEMPTY Interrupt Mask
9
1
read-only
TXRDY
TXRDY Interrupt Mask
1
1
read-only
UNRE
SPI Underrun Error Interrupt Mask
10
1
read-only
MAN
Manchester Configuration Register
0x50
32
read-write
n
0x0
0x0
DRIFT
Drift Compensation
30
1
read-write
ONE
Must Be Set to 1
29
1
read-write
RX_MPOL
Receiver Manchester Polarity
28
1
read-write
RX_PL
Receiver Preamble Length
16
4
read-write
RX_PP
Receiver Preamble Pattern detected
24
2
read-write
ALL_ONE
The preamble is composed of '1's
0x0
ALL_ZERO
The preamble is composed of '0's
0x1
ZERO_ONE
The preamble is composed of '01's
0x2
ONE_ZERO
The preamble is composed of '10's
0x3
TX_MPOL
Transmitter Manchester Polarity
12
1
read-write
TX_PL
Transmitter Preamble Length
0
4
read-write
TX_PP
Transmitter Preamble Pattern
8
2
read-write
ALL_ONE
The preamble is composed of '1's
0x0
ALL_ZERO
The preamble is composed of '0's
0x1
ZERO_ONE
The preamble is composed of '01's
0x2
ONE_ZERO
The preamble is composed of '10's
0x3
MR
Mode Register
0x4
32
read-write
n
0x0
0x0
CHMODE
Channel Mode
14
2
read-write
NORMAL
Normal mode
0x0
AUTOMATIC
Automatic Echo. Receiver input is connected to the TXD pin.
0x1
LOCAL_LOOPBACK
Local Loopback. Transmitter output is connected to the Receiver Input.
0x2
REMOTE_LOOPBACK
Remote Loopback. RXD pin is internally connected to the TXD pin.
0x3
CHRL
Character Length
6
2
read-write
5_BIT
Character length is 5 bits
0x0
6_BIT
Character length is 6 bits
0x1
7_BIT
Character length is 7 bits
0x2
8_BIT
Character length is 8 bits
0x3
CLKO
Clock Output Select
18
1
read-write
DSNACK
Disable Successive NACK
21
1
read-write
FILTER
Receive Line Filter
28
1
read-write
INACK
Inhibit Non Acknowledge
20
1
read-write
INVDATA
Inverted Data
23
1
read-write
MAN
Manchester Encoder/Decoder Enable
29
1
read-write
MAX_ITERATION
Maximum Number of Automatic Iteration
24
3
read-write
MODE9
9-bit Character Length
17
1
read-write
MODSYNC
Manchester Synchronization Mode
30
1
read-write
MSBF
Bit Order
16
1
read-write
NBSTOP
Number of Stop Bits
12
2
read-write
1_BIT
1 stop bit
0x0
1_5_BIT
1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
0x1
2_BIT
2 stop bits
0x2
ONEBIT
Start Frame Delimiter Selector
31
1
read-write
OVER
Oversampling Mode
19
1
read-write
PAR
Parity Type
9
3
read-write
EVEN
Even parity
0x0
ODD
Odd parity
0x1
SPACE
Parity forced to 0 (Space)
0x2
MARK
Parity forced to 1 (Mark)
0x3
NO
No parity
0x4
MULTIDROP
Multidrop mode
0x6
SYNC
Synchronous Mode Select
8
1
read-write
USART_MODE
USART Mode of Operation
0
4
read-write
NORMAL
Normal mode
0x0
RS485
RS485
0x1
HW_HANDSHAKING
Hardware Handshaking
0x2
IS07816_T_0
IS07816 Protocol: T = 0
0x4
IS07816_T_1
IS07816 Protocol: T = 1
0x6
IRDA
IrDA
0x8
SPI_MASTER
SPI master
0xE
SPI_SLAVE
SPI Slave
0xF
USCLKS
Clock Selection
4
2
read-write
MCK
Peripheral clock is selected
0x0
DIV
Peripheral clock divided (DIV=8) is selected
0x1
SCK
Serial clock (SCK) is selected
0x3
VAR_SYNC
Variable Synchronization of Command/Data Sync Start Frame Delimiter
22
1
read-write
MR_SPI_MODE
Mode Register
SPI_MODE
0x4
32
read-write
n
0x0
0x0
CHRL
Character Length
6
2
read-write
8_BIT
Character length is 8 bits
0x3
CLKO
Clock Output Select
18
1
read-write
CPHA
SPI Clock Phase
8
1
read-write
CPOL
SPI Clock Polarity
16
1
read-write
USART_MODE
USART Mode of Operation
0
4
read-write
SPI_MASTER
SPI master
0xE
SPI_SLAVE
SPI Slave
0xF
USCLKS
Clock Selection
4
2
read-write
MCK
Peripheral clock is selected
0x0
DIV
Peripheral clock divided (DIV=8) is selected
0x1
SCK
Serial Clock SLK is selected
0x3
WRDBT
Wait Read Data Before Transfer
20
1
read-write
NER
Number of Errors Register
0x44
32
read-only
n
0x0
0x0
NB_ERRORS
Number of Errors
0
8
read-only
PTCR
Transfer Control Register
0x120
32
write-only
n
0x0
0x0
RXTDIS
Receiver Transfer Disable
1
1
write-only
RXTEN
Receiver Transfer Enable
0
1
write-only
TXTDIS
Transmitter Transfer Disable
9
1
write-only
TXTEN
Transmitter Transfer Enable
8
1
write-only
PTSR
Transfer Status Register
0x124
32
read-only
n
0x0
0x0
RXTEN
Receiver Transfer Enable
0
1
read-only
TXTEN
Transmitter Transfer Enable
8
1
read-only
RCR
Receive Counter Register
0x104
32
read-write
n
0x0
0x0
RXCTR
Receive Counter Register
0
16
read-write
RHR
Receive Holding Register
0x18
32
read-only
n
0x0
0x0
RXCHR
Received Character
0
9
read-only
RXSYNH
Received Sync
15
1
read-only
RNCR
Receive Next Counter Register
0x114
32
read-write
n
0x0
0x0
RXNCTR
Receive Next Counter
0
16
read-write
RNPR
Receive Next Pointer Register
0x110
32
read-write
n
0x0
0x0
RXNPTR
Receive Next Pointer
0
32
read-write
RPR
Receive Pointer Register
0x100
32
read-write
n
0x0
0x0
RXPTR
Receive Pointer Register
0
32
read-write
RTOR
Receiver Time-out Register
0x24
32
read-write
n
0x0
0x0
TO
Time-out Value
0
16
read-write
TCR
Transmit Counter Register
0x10C
32
read-write
n
0x0
0x0
TXCTR
Transmit Counter Register
0
16
read-write
THR
Transmit Holding Register
0x1C
32
write-only
n
0x0
0x0
TXCHR
Character to be Transmitted
0
9
write-only
TXSYNH
Sync Field to be Transmitted
15
1
write-only
TNCR
Transmit Next Counter Register
0x11C
32
read-write
n
0x0
0x0
TXNCTR
Transmit Counter Next
0
16
read-write
TNPR
Transmit Next Pointer Register
0x118
32
read-write
n
0x0
0x0
TXNPTR
Transmit Next Pointer
0
32
read-write
TPR
Transmit Pointer Register
0x108
32
read-write
n
0x0
0x0
TXPTR
Transmit Counter Register
0
32
read-write
TTGR
Transmitter Timeguard Register
0x28
32
read-write
n
0x0
0x0
TG
Timeguard Value
0
8
read-write
WPMR
Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protection Enable
0
1
read-write
WPKEY
Write Protection Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
0x555341
WPSR
Write Protection Status Register
0xE8
32
read-only
n
0x0
0x0
WPVS
Write Protection Violation Status
0
1
read-only
WPVSRC
Write Protection Violation Source
8
16
read-only
USART2
Universal Synchronous Asynchronous Receiver Transmitter 2
USART
0x0
0x0
0x50
registers
n
USART2
16
BRGR
Baud Rate Generator Register
0x20
32
read-write
n
0x0
0x0
CD
Clock Divider
0
16
read-write
FP
Fractional Part
16
3
read-write
CR
Control Register
0x0
32
write-only
n
0x0
0x0
RETTO
Rearm Time-out
15
1
write-only
RSTIT
Reset Iterations
13
1
write-only
RSTNACK
Reset Non Acknowledge
14
1
write-only
RSTRX
Reset Receiver
2
1
write-only
RSTSTA
Reset Status Bits
8
1
write-only
RSTTX
Reset Transmitter
3
1
write-only
RTSDIS
Request to Send Disable
19
1
write-only
RTSEN
Request to Send Enable
18
1
write-only
RXDIS
Receiver Disable
5
1
write-only
RXEN
Receiver Enable
4
1
write-only
SENDA
Send Address
12
1
write-only
STPBRK
Stop Break
10
1
write-only
STTBRK
Start Break
9
1
write-only
STTTO
Start Time-out
11
1
write-only
TXDIS
Transmitter Disable
7
1
write-only
TXEN
Transmitter Enable
6
1
write-only
CR_SPI_MODE
Control Register
SPI_MODE
0x0
32
write-only
n
0x0
0x0
FCS
Force SPI Chip Select
18
1
write-only
RCS
Release SPI Chip Select
19
1
write-only
RSTRX
Reset Receiver
2
1
write-only
RSTSTA
Reset Status Bits
8
1
write-only
RSTTX
Reset Transmitter
3
1
write-only
RXDIS
Receiver Disable
5
1
write-only
RXEN
Receiver Enable
4
1
write-only
TXDIS
Transmitter Disable
7
1
write-only
TXEN
Transmitter Enable
6
1
write-only
CSR
Channel Status Register
0x14
32
read-only
n
0x0
0x0
CTS
Image of CTS Input
23
1
read-only
CTSIC
Clear to Send Input Change Flag (clear on read)
19
1
read-only
ENDRX
End of RX Buffer
3
1
read-only
ENDTX
End of TX Buffer
4
1
read-only
FRAME
Framing Error
6
1
read-only
ITER
Max Number of Repetitions Reached
10
1
read-only
MANERR
Manchester Error
24
1
read-only
NACK
Non Acknowledge Interrupt
13
1
read-only
OVRE
Overrun Error
5
1
read-only
PARE
Parity Error
7
1
read-only
RXBRK
Break Received/End of Break
2
1
read-only
RXBUFF
RX Buffer Full
12
1
read-only
RXRDY
Receiver Ready (automatically set / reset)
0
1
read-only
TIMEOUT
Receiver Time-out
8
1
read-only
TXBUFE
TX Buffer Empty
11
1
read-only
TXEMPTY
Transmitter Empty (automatically set / reset)
9
1
read-only
TXRDY
Transmitter Ready (automatically set / reset)
1
1
read-only
CSR_SPI_MODE
Channel Status Register
SPI_MODE
0x14
32
read-only
n
0x0
0x0
ENDRX
3
1
read-only
ENDTX
4
1
read-only
OVRE
Overrun Error
5
1
read-only
RXBUFF
12
1
read-only
RXRDY
Receiver Ready (automatically set / reset)
0
1
read-only
TXBUFE
11
1
read-only
TXEMPTY
Transmitter Empty (automatically set / reset)
9
1
read-only
TXRDY
Transmitter Ready (automatically set / reset)
1
1
read-only
UNRE
Underrun Error
10
1
read-only
FIDI
FI DI Ratio Register
0x40
32
read-write
n
0x0
0x0
FI_DI_RATIO
FI Over DI Ratio Value
0
11
read-write
IDR
Interrupt Disable Register
0xC
32
write-only
n
0x0
0x0
CTSIC
Clear to Send Input Change Interrupt Disable
19
1
write-only
ENDRX
End of Receive Buffer Transfer Interrupt Disable (available in all USART modes of operation)
3
1
write-only
ENDTX
End of Transmit Buffer Interrupt Disable (available in all USART modes of operation)
4
1
write-only
FRAME
Framing Error Interrupt Disable
6
1
write-only
ITER
Max Number of Repetitions Reached Interrupt Disable
10
1
write-only
MANE
Manchester Error Interrupt Disable
24
1
write-only
NACK
Non Acknowledge Interrupt Disable
13
1
write-only
OVRE
Overrun Error Interrupt Enable
5
1
write-only
PARE
Parity Error Interrupt Disable
7
1
write-only
RXBRK
Receiver Break Interrupt Disable
2
1
write-only
RXBUFF
Receive Buffer Full Interrupt Disable (available in all USART modes of operation)
12
1
write-only
RXRDY
RXRDY Interrupt Disable
0
1
write-only
TIMEOUT
Time-out Interrupt Disable
8
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Disable (available in all USART modes of operation)
11
1
write-only
TXEMPTY
TXEMPTY Interrupt Disable
9
1
write-only
TXRDY
TXRDY Interrupt Disable
1
1
write-only
IDR_SPI_MODE
Interrupt Disable Register
SPI_MODE
0xC
32
write-only
n
0x0
0x0
ENDRX
3
1
write-only
ENDTX
4
1
write-only
OVRE
Overrun Error Interrupt Disable
5
1
write-only
RXBUFF
12
1
write-only
RXRDY
RXRDY Interrupt Disable
0
1
write-only
TXBUFE
11
1
write-only
TXEMPTY
TXEMPTY Interrupt Disable
9
1
write-only
TXRDY
TXRDY Interrupt Disable
1
1
write-only
UNRE
SPI Underrun Error Interrupt Disable
10
1
write-only
IER
Interrupt Enable Register
0x8
32
write-only
n
0x0
0x0
CTSIC
Clear to Send Input Change Interrupt Enable
19
1
write-only
ENDRX
End of Receive Buffer Interrupt Enable (available in all USART modes of operation)
3
1
write-only
ENDTX
End of Transmit Buffer Interrupt Enable (available in all USART modes of operation)
4
1
write-only
FRAME
Framing Error Interrupt Enable
6
1
write-only
ITER
Max number of Repetitions Reached Interrupt Enable
10
1
write-only
MANE
Manchester Error Interrupt Enable
24
1
write-only
NACK
Non Acknowledge Interrupt Enable
13
1
write-only
OVRE
Overrun Error Interrupt Enable
5
1
write-only
PARE
Parity Error Interrupt Enable
7
1
write-only
RXBRK
Receiver Break Interrupt Enable
2
1
write-only
RXBUFF
Receive Buffer Full Interrupt Enable (available in all USART modes of operation)
12
1
write-only
RXRDY
RXRDY Interrupt Enable
0
1
write-only
TIMEOUT
Time-out Interrupt Enable
8
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation)
11
1
write-only
TXEMPTY
TXEMPTY Interrupt Enable
9
1
write-only
TXRDY
TXRDY Interrupt Enable
1
1
write-only
IER_SPI_MODE
Interrupt Enable Register
SPI_MODE
0x8
32
write-only
n
0x0
0x0
ENDRX
3
1
write-only
ENDTX
4
1
write-only
OVRE
Overrun Error Interrupt Enable
5
1
write-only
RXBUFF
12
1
write-only
RXRDY
RXRDY Interrupt Enable
0
1
write-only
TXBUFE
11
1
write-only
TXEMPTY
TXEMPTY Interrupt Enable
9
1
write-only
TXRDY
TXRDY Interrupt Enable
1
1
write-only
UNRE
SPI Underrun Error Interrupt Enable
10
1
write-only
IF
IrDA Filter Register
0x4C
32
read-write
n
0x0
0x0
IRDA_FILTER
IrDA Filter
0
8
read-write
IMR
Interrupt Mask Register
0x10
32
read-only
n
0x0
0x0
CTSIC
Clear to Send Input Change Interrupt Mask
19
1
read-only
ENDRX
End of Receive Buffer Interrupt Mask (available in all USART modes of operation)
3
1
read-only
ENDTX
End of Transmit Buffer Interrupt Mask (available in all USART modes of operation)
4
1
read-only
FRAME
Framing Error Interrupt Mask
6
1
read-only
ITER
Max Number of Repetitions Reached Interrupt Mask
10
1
read-only
MANE
Manchester Error Interrupt Mask
24
1
read-only
NACK
Non Acknowledge Interrupt Mask
13
1
read-only
OVRE
Overrun Error Interrupt Mask
5
1
read-only
PARE
Parity Error Interrupt Mask
7
1
read-only
RXBRK
Receiver Break Interrupt Mask
2
1
read-only
RXBUFF
Receive Buffer Full Interrupt Mask (available in all USART modes of operation)
12
1
read-only
RXRDY
RXRDY Interrupt Mask
0
1
read-only
TIMEOUT
Time-out Interrupt Mask
8
1
read-only
TXBUFE
Transmit Buffer Empty Interrupt Mask (available in all USART modes of operation)
11
1
read-only
TXEMPTY
TXEMPTY Interrupt Mask
9
1
read-only
TXRDY
TXRDY Interrupt Mask
1
1
read-only
IMR_SPI_MODE
Interrupt Mask Register
SPI_MODE
0x10
32
read-only
n
0x0
0x0
ENDRX
3
1
read-only
ENDTX
4
1
read-only
OVRE
Overrun Error Interrupt Mask
5
1
read-only
RXBUFF
12
1
read-only
RXRDY
RXRDY Interrupt Mask
0
1
read-only
TXBUFE
11
1
read-only
TXEMPTY
TXEMPTY Interrupt Mask
9
1
read-only
TXRDY
TXRDY Interrupt Mask
1
1
read-only
UNRE
SPI Underrun Error Interrupt Mask
10
1
read-only
MAN
Manchester Configuration Register
0x50
32
read-write
n
0x0
0x0
DRIFT
Drift Compensation
30
1
read-write
ONE
Must Be Set to 1
29
1
read-write
RX_MPOL
Receiver Manchester Polarity
28
1
read-write
RX_PL
Receiver Preamble Length
16
4
read-write
RX_PP
Receiver Preamble Pattern detected
24
2
read-write
ALL_ONE
The preamble is composed of '1's
0x0
ALL_ZERO
The preamble is composed of '0's
0x1
ZERO_ONE
The preamble is composed of '01's
0x2
ONE_ZERO
The preamble is composed of '10's
0x3
TX_MPOL
Transmitter Manchester Polarity
12
1
read-write
TX_PL
Transmitter Preamble Length
0
4
read-write
TX_PP
Transmitter Preamble Pattern
8
2
read-write
ALL_ONE
The preamble is composed of '1's
0x0
ALL_ZERO
The preamble is composed of '0's
0x1
ZERO_ONE
The preamble is composed of '01's
0x2
ONE_ZERO
The preamble is composed of '10's
0x3
MR
Mode Register
0x4
32
read-write
n
0x0
0x0
CHMODE
Channel Mode
14
2
read-write
NORMAL
Normal mode
0x0
AUTOMATIC
Automatic Echo. Receiver input is connected to the TXD pin.
0x1
LOCAL_LOOPBACK
Local Loopback. Transmitter output is connected to the Receiver Input.
0x2
REMOTE_LOOPBACK
Remote Loopback. RXD pin is internally connected to the TXD pin.
0x3
CHRL
Character Length
6
2
read-write
5_BIT
Character length is 5 bits
0x0
6_BIT
Character length is 6 bits
0x1
7_BIT
Character length is 7 bits
0x2
8_BIT
Character length is 8 bits
0x3
CLKO
Clock Output Select
18
1
read-write
DSNACK
Disable Successive NACK
21
1
read-write
FILTER
Receive Line Filter
28
1
read-write
INACK
Inhibit Non Acknowledge
20
1
read-write
INVDATA
Inverted Data
23
1
read-write
MAN
Manchester Encoder/Decoder Enable
29
1
read-write
MAX_ITERATION
Maximum Number of Automatic Iteration
24
3
read-write
MODE9
9-bit Character Length
17
1
read-write
MODSYNC
Manchester Synchronization Mode
30
1
read-write
MSBF
Bit Order
16
1
read-write
NBSTOP
Number of Stop Bits
12
2
read-write
1_BIT
1 stop bit
0x0
1_5_BIT
1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
0x1
2_BIT
2 stop bits
0x2
ONEBIT
Start Frame Delimiter Selector
31
1
read-write
OVER
Oversampling Mode
19
1
read-write
PAR
Parity Type
9
3
read-write
EVEN
Even parity
0x0
ODD
Odd parity
0x1
SPACE
Parity forced to 0 (Space)
0x2
MARK
Parity forced to 1 (Mark)
0x3
NO
No parity
0x4
MULTIDROP
Multidrop mode
0x6
SYNC
Synchronous Mode Select
8
1
read-write
USART_MODE
USART Mode of Operation
0
4
read-write
NORMAL
Normal mode
0x0
RS485
RS485
0x1
HW_HANDSHAKING
Hardware Handshaking
0x2
IS07816_T_0
IS07816 Protocol: T = 0
0x4
IS07816_T_1
IS07816 Protocol: T = 1
0x6
IRDA
IrDA
0x8
SPI_MASTER
SPI master
0xE
SPI_SLAVE
SPI Slave
0xF
USCLKS
Clock Selection
4
2
read-write
MCK
Peripheral clock is selected
0x0
DIV
Peripheral clock divided (DIV=8) is selected
0x1
SCK
Serial clock (SCK) is selected
0x3
VAR_SYNC
Variable Synchronization of Command/Data Sync Start Frame Delimiter
22
1
read-write
MR_SPI_MODE
Mode Register
SPI_MODE
0x4
32
read-write
n
0x0
0x0
CHRL
Character Length
6
2
read-write
8_BIT
Character length is 8 bits
0x3
CLKO
Clock Output Select
18
1
read-write
CPHA
SPI Clock Phase
8
1
read-write
CPOL
SPI Clock Polarity
16
1
read-write
USART_MODE
USART Mode of Operation
0
4
read-write
SPI_MASTER
SPI master
0xE
SPI_SLAVE
SPI Slave
0xF
USCLKS
Clock Selection
4
2
read-write
MCK
Peripheral clock is selected
0x0
DIV
Peripheral clock divided (DIV=8) is selected
0x1
SCK
Serial Clock SLK is selected
0x3
WRDBT
Wait Read Data Before Transfer
20
1
read-write
NER
Number of Errors Register
0x44
32
read-only
n
0x0
0x0
NB_ERRORS
Number of Errors
0
8
read-only
PTCR
Transfer Control Register
0x120
32
write-only
n
0x0
0x0
RXTDIS
Receiver Transfer Disable
1
1
write-only
RXTEN
Receiver Transfer Enable
0
1
write-only
TXTDIS
Transmitter Transfer Disable
9
1
write-only
TXTEN
Transmitter Transfer Enable
8
1
write-only
PTSR
Transfer Status Register
0x124
32
read-only
n
0x0
0x0
RXTEN
Receiver Transfer Enable
0
1
read-only
TXTEN
Transmitter Transfer Enable
8
1
read-only
RCR
Receive Counter Register
0x104
32
read-write
n
0x0
0x0
RXCTR
Receive Counter Register
0
16
read-write
RHR
Receive Holding Register
0x18
32
read-only
n
0x0
0x0
RXCHR
Received Character
0
9
read-only
RXSYNH
Received Sync
15
1
read-only
RNCR
Receive Next Counter Register
0x114
32
read-write
n
0x0
0x0
RXNCTR
Receive Next Counter
0
16
read-write
RNPR
Receive Next Pointer Register
0x110
32
read-write
n
0x0
0x0
RXNPTR
Receive Next Pointer
0
32
read-write
RPR
Receive Pointer Register
0x100
32
read-write
n
0x0
0x0
RXPTR
Receive Pointer Register
0
32
read-write
RTOR
Receiver Time-out Register
0x24
32
read-write
n
0x0
0x0
TO
Time-out Value
0
16
read-write
TCR
Transmit Counter Register
0x10C
32
read-write
n
0x0
0x0
TXCTR
Transmit Counter Register
0
16
read-write
THR
Transmit Holding Register
0x1C
32
write-only
n
0x0
0x0
TXCHR
Character to be Transmitted
0
9
write-only
TXSYNH
Sync Field to be Transmitted
15
1
write-only
TNCR
Transmit Next Counter Register
0x11C
32
read-write
n
0x0
0x0
TXNCTR
Transmit Counter Next
0
16
read-write
TNPR
Transmit Next Pointer Register
0x118
32
read-write
n
0x0
0x0
TXNPTR
Transmit Next Pointer
0
32
read-write
TPR
Transmit Pointer Register
0x108
32
read-write
n
0x0
0x0
TXPTR
Transmit Counter Register
0
32
read-write
TTGR
Transmitter Timeguard Register
0x28
32
read-write
n
0x0
0x0
TG
Timeguard Value
0
8
read-write
WPMR
Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protection Enable
0
1
read-write
WPKEY
Write Protection Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
0x555341
WPSR
Write Protection Status Register
0xE8
32
read-only
n
0x0
0x0
WPVS
Write Protection Violation Status
0
1
read-only
WPVSRC
Write Protection Violation Source
8
16
read-only
USART3
Universal Synchronous Asynchronous Receiver Transmitter 3
USART
0x0
0x0
0x50
registers
n
USART3
17
BRGR
Baud Rate Generator Register
0x20
32
read-write
n
0x0
0x0
CD
Clock Divider
0
16
read-write
FP
Fractional Part
16
3
read-write
CR
Control Register
0x0
32
write-only
n
0x0
0x0
RETTO
Rearm Time-out
15
1
write-only
RSTIT
Reset Iterations
13
1
write-only
RSTNACK
Reset Non Acknowledge
14
1
write-only
RSTRX
Reset Receiver
2
1
write-only
RSTSTA
Reset Status Bits
8
1
write-only
RSTTX
Reset Transmitter
3
1
write-only
RTSDIS
Request to Send Disable
19
1
write-only
RTSEN
Request to Send Enable
18
1
write-only
RXDIS
Receiver Disable
5
1
write-only
RXEN
Receiver Enable
4
1
write-only
SENDA
Send Address
12
1
write-only
STPBRK
Stop Break
10
1
write-only
STTBRK
Start Break
9
1
write-only
STTTO
Start Time-out
11
1
write-only
TXDIS
Transmitter Disable
7
1
write-only
TXEN
Transmitter Enable
6
1
write-only
CR_SPI_MODE
Control Register
SPI_MODE
0x0
32
write-only
n
0x0
0x0
FCS
Force SPI Chip Select
18
1
write-only
RCS
Release SPI Chip Select
19
1
write-only
RSTRX
Reset Receiver
2
1
write-only
RSTSTA
Reset Status Bits
8
1
write-only
RSTTX
Reset Transmitter
3
1
write-only
RXDIS
Receiver Disable
5
1
write-only
RXEN
Receiver Enable
4
1
write-only
TXDIS
Transmitter Disable
7
1
write-only
TXEN
Transmitter Enable
6
1
write-only
CSR
Channel Status Register
0x14
32
read-only
n
0x0
0x0
CTS
Image of CTS Input
23
1
read-only
CTSIC
Clear to Send Input Change Flag (clear on read)
19
1
read-only
ENDRX
End of RX Buffer
3
1
read-only
ENDTX
End of TX Buffer
4
1
read-only
FRAME
Framing Error
6
1
read-only
ITER
Max Number of Repetitions Reached
10
1
read-only
MANERR
Manchester Error
24
1
read-only
NACK
Non Acknowledge Interrupt
13
1
read-only
OVRE
Overrun Error
5
1
read-only
PARE
Parity Error
7
1
read-only
RXBRK
Break Received/End of Break
2
1
read-only
RXBUFF
RX Buffer Full
12
1
read-only
RXRDY
Receiver Ready (automatically set / reset)
0
1
read-only
TIMEOUT
Receiver Time-out
8
1
read-only
TXBUFE
TX Buffer Empty
11
1
read-only
TXEMPTY
Transmitter Empty (automatically set / reset)
9
1
read-only
TXRDY
Transmitter Ready (automatically set / reset)
1
1
read-only
CSR_SPI_MODE
Channel Status Register
SPI_MODE
0x14
32
read-only
n
0x0
0x0
ENDRX
3
1
read-only
ENDTX
4
1
read-only
OVRE
Overrun Error
5
1
read-only
RXBUFF
12
1
read-only
RXRDY
Receiver Ready (automatically set / reset)
0
1
read-only
TXBUFE
11
1
read-only
TXEMPTY
Transmitter Empty (automatically set / reset)
9
1
read-only
TXRDY
Transmitter Ready (automatically set / reset)
1
1
read-only
UNRE
Underrun Error
10
1
read-only
FIDI
FI DI Ratio Register
0x40
32
read-write
n
0x0
0x0
FI_DI_RATIO
FI Over DI Ratio Value
0
11
read-write
IDR
Interrupt Disable Register
0xC
32
write-only
n
0x0
0x0
CTSIC
Clear to Send Input Change Interrupt Disable
19
1
write-only
ENDRX
End of Receive Buffer Transfer Interrupt Disable (available in all USART modes of operation)
3
1
write-only
ENDTX
End of Transmit Buffer Interrupt Disable (available in all USART modes of operation)
4
1
write-only
FRAME
Framing Error Interrupt Disable
6
1
write-only
ITER
Max Number of Repetitions Reached Interrupt Disable
10
1
write-only
MANE
Manchester Error Interrupt Disable
24
1
write-only
NACK
Non Acknowledge Interrupt Disable
13
1
write-only
OVRE
Overrun Error Interrupt Enable
5
1
write-only
PARE
Parity Error Interrupt Disable
7
1
write-only
RXBRK
Receiver Break Interrupt Disable
2
1
write-only
RXBUFF
Receive Buffer Full Interrupt Disable (available in all USART modes of operation)
12
1
write-only
RXRDY
RXRDY Interrupt Disable
0
1
write-only
TIMEOUT
Time-out Interrupt Disable
8
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Disable (available in all USART modes of operation)
11
1
write-only
TXEMPTY
TXEMPTY Interrupt Disable
9
1
write-only
TXRDY
TXRDY Interrupt Disable
1
1
write-only
IDR_SPI_MODE
Interrupt Disable Register
SPI_MODE
0xC
32
write-only
n
0x0
0x0
ENDRX
3
1
write-only
ENDTX
4
1
write-only
OVRE
Overrun Error Interrupt Disable
5
1
write-only
RXBUFF
12
1
write-only
RXRDY
RXRDY Interrupt Disable
0
1
write-only
TXBUFE
11
1
write-only
TXEMPTY
TXEMPTY Interrupt Disable
9
1
write-only
TXRDY
TXRDY Interrupt Disable
1
1
write-only
UNRE
SPI Underrun Error Interrupt Disable
10
1
write-only
IER
Interrupt Enable Register
0x8
32
write-only
n
0x0
0x0
CTSIC
Clear to Send Input Change Interrupt Enable
19
1
write-only
ENDRX
End of Receive Buffer Interrupt Enable (available in all USART modes of operation)
3
1
write-only
ENDTX
End of Transmit Buffer Interrupt Enable (available in all USART modes of operation)
4
1
write-only
FRAME
Framing Error Interrupt Enable
6
1
write-only
ITER
Max number of Repetitions Reached Interrupt Enable
10
1
write-only
MANE
Manchester Error Interrupt Enable
24
1
write-only
NACK
Non Acknowledge Interrupt Enable
13
1
write-only
OVRE
Overrun Error Interrupt Enable
5
1
write-only
PARE
Parity Error Interrupt Enable
7
1
write-only
RXBRK
Receiver Break Interrupt Enable
2
1
write-only
RXBUFF
Receive Buffer Full Interrupt Enable (available in all USART modes of operation)
12
1
write-only
RXRDY
RXRDY Interrupt Enable
0
1
write-only
TIMEOUT
Time-out Interrupt Enable
8
1
write-only
TXBUFE
Transmit Buffer Empty Interrupt Enable (available in all USART modes of operation)
11
1
write-only
TXEMPTY
TXEMPTY Interrupt Enable
9
1
write-only
TXRDY
TXRDY Interrupt Enable
1
1
write-only
IER_SPI_MODE
Interrupt Enable Register
SPI_MODE
0x8
32
write-only
n
0x0
0x0
ENDRX
3
1
write-only
ENDTX
4
1
write-only
OVRE
Overrun Error Interrupt Enable
5
1
write-only
RXBUFF
12
1
write-only
RXRDY
RXRDY Interrupt Enable
0
1
write-only
TXBUFE
11
1
write-only
TXEMPTY
TXEMPTY Interrupt Enable
9
1
write-only
TXRDY
TXRDY Interrupt Enable
1
1
write-only
UNRE
SPI Underrun Error Interrupt Enable
10
1
write-only
IF
IrDA Filter Register
0x4C
32
read-write
n
0x0
0x0
IRDA_FILTER
IrDA Filter
0
8
read-write
IMR
Interrupt Mask Register
0x10
32
read-only
n
0x0
0x0
CTSIC
Clear to Send Input Change Interrupt Mask
19
1
read-only
ENDRX
End of Receive Buffer Interrupt Mask (available in all USART modes of operation)
3
1
read-only
ENDTX
End of Transmit Buffer Interrupt Mask (available in all USART modes of operation)
4
1
read-only
FRAME
Framing Error Interrupt Mask
6
1
read-only
ITER
Max Number of Repetitions Reached Interrupt Mask
10
1
read-only
MANE
Manchester Error Interrupt Mask
24
1
read-only
NACK
Non Acknowledge Interrupt Mask
13
1
read-only
OVRE
Overrun Error Interrupt Mask
5
1
read-only
PARE
Parity Error Interrupt Mask
7
1
read-only
RXBRK
Receiver Break Interrupt Mask
2
1
read-only
RXBUFF
Receive Buffer Full Interrupt Mask (available in all USART modes of operation)
12
1
read-only
RXRDY
RXRDY Interrupt Mask
0
1
read-only
TIMEOUT
Time-out Interrupt Mask
8
1
read-only
TXBUFE
Transmit Buffer Empty Interrupt Mask (available in all USART modes of operation)
11
1
read-only
TXEMPTY
TXEMPTY Interrupt Mask
9
1
read-only
TXRDY
TXRDY Interrupt Mask
1
1
read-only
IMR_SPI_MODE
Interrupt Mask Register
SPI_MODE
0x10
32
read-only
n
0x0
0x0
ENDRX
3
1
read-only
ENDTX
4
1
read-only
OVRE
Overrun Error Interrupt Mask
5
1
read-only
RXBUFF
12
1
read-only
RXRDY
RXRDY Interrupt Mask
0
1
read-only
TXBUFE
11
1
read-only
TXEMPTY
TXEMPTY Interrupt Mask
9
1
read-only
TXRDY
TXRDY Interrupt Mask
1
1
read-only
UNRE
SPI Underrun Error Interrupt Mask
10
1
read-only
MAN
Manchester Configuration Register
0x50
32
read-write
n
0x0
0x0
DRIFT
Drift Compensation
30
1
read-write
ONE
Must Be Set to 1
29
1
read-write
RX_MPOL
Receiver Manchester Polarity
28
1
read-write
RX_PL
Receiver Preamble Length
16
4
read-write
RX_PP
Receiver Preamble Pattern detected
24
2
read-write
ALL_ONE
The preamble is composed of '1's
0x0
ALL_ZERO
The preamble is composed of '0's
0x1
ZERO_ONE
The preamble is composed of '01's
0x2
ONE_ZERO
The preamble is composed of '10's
0x3
TX_MPOL
Transmitter Manchester Polarity
12
1
read-write
TX_PL
Transmitter Preamble Length
0
4
read-write
TX_PP
Transmitter Preamble Pattern
8
2
read-write
ALL_ONE
The preamble is composed of '1's
0x0
ALL_ZERO
The preamble is composed of '0's
0x1
ZERO_ONE
The preamble is composed of '01's
0x2
ONE_ZERO
The preamble is composed of '10's
0x3
MR
Mode Register
0x4
32
read-write
n
0x0
0x0
CHMODE
Channel Mode
14
2
read-write
NORMAL
Normal mode
0x0
AUTOMATIC
Automatic Echo. Receiver input is connected to the TXD pin.
0x1
LOCAL_LOOPBACK
Local Loopback. Transmitter output is connected to the Receiver Input.
0x2
REMOTE_LOOPBACK
Remote Loopback. RXD pin is internally connected to the TXD pin.
0x3
CHRL
Character Length
6
2
read-write
5_BIT
Character length is 5 bits
0x0
6_BIT
Character length is 6 bits
0x1
7_BIT
Character length is 7 bits
0x2
8_BIT
Character length is 8 bits
0x3
CLKO
Clock Output Select
18
1
read-write
DSNACK
Disable Successive NACK
21
1
read-write
FILTER
Receive Line Filter
28
1
read-write
INACK
Inhibit Non Acknowledge
20
1
read-write
INVDATA
Inverted Data
23
1
read-write
MAN
Manchester Encoder/Decoder Enable
29
1
read-write
MAX_ITERATION
Maximum Number of Automatic Iteration
24
3
read-write
MODE9
9-bit Character Length
17
1
read-write
MODSYNC
Manchester Synchronization Mode
30
1
read-write
MSBF
Bit Order
16
1
read-write
NBSTOP
Number of Stop Bits
12
2
read-write
1_BIT
1 stop bit
0x0
1_5_BIT
1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)
0x1
2_BIT
2 stop bits
0x2
ONEBIT
Start Frame Delimiter Selector
31
1
read-write
OVER
Oversampling Mode
19
1
read-write
PAR
Parity Type
9
3
read-write
EVEN
Even parity
0x0
ODD
Odd parity
0x1
SPACE
Parity forced to 0 (Space)
0x2
MARK
Parity forced to 1 (Mark)
0x3
NO
No parity
0x4
MULTIDROP
Multidrop mode
0x6
SYNC
Synchronous Mode Select
8
1
read-write
USART_MODE
USART Mode of Operation
0
4
read-write
NORMAL
Normal mode
0x0
RS485
RS485
0x1
HW_HANDSHAKING
Hardware Handshaking
0x2
IS07816_T_0
IS07816 Protocol: T = 0
0x4
IS07816_T_1
IS07816 Protocol: T = 1
0x6
IRDA
IrDA
0x8
SPI_MASTER
SPI master
0xE
SPI_SLAVE
SPI Slave
0xF
USCLKS
Clock Selection
4
2
read-write
MCK
Peripheral clock is selected
0x0
DIV
Peripheral clock divided (DIV=8) is selected
0x1
SCK
Serial clock (SCK) is selected
0x3
VAR_SYNC
Variable Synchronization of Command/Data Sync Start Frame Delimiter
22
1
read-write
MR_SPI_MODE
Mode Register
SPI_MODE
0x4
32
read-write
n
0x0
0x0
CHRL
Character Length
6
2
read-write
8_BIT
Character length is 8 bits
0x3
CLKO
Clock Output Select
18
1
read-write
CPHA
SPI Clock Phase
8
1
read-write
CPOL
SPI Clock Polarity
16
1
read-write
USART_MODE
USART Mode of Operation
0
4
read-write
SPI_MASTER
SPI master
0xE
SPI_SLAVE
SPI Slave
0xF
USCLKS
Clock Selection
4
2
read-write
MCK
Peripheral clock is selected
0x0
DIV
Peripheral clock divided (DIV=8) is selected
0x1
SCK
Serial Clock SLK is selected
0x3
WRDBT
Wait Read Data Before Transfer
20
1
read-write
NER
Number of Errors Register
0x44
32
read-only
n
0x0
0x0
NB_ERRORS
Number of Errors
0
8
read-only
PTCR
Transfer Control Register
0x120
32
write-only
n
0x0
0x0
RXTDIS
Receiver Transfer Disable
1
1
write-only
RXTEN
Receiver Transfer Enable
0
1
write-only
TXTDIS
Transmitter Transfer Disable
9
1
write-only
TXTEN
Transmitter Transfer Enable
8
1
write-only
PTSR
Transfer Status Register
0x124
32
read-only
n
0x0
0x0
RXTEN
Receiver Transfer Enable
0
1
read-only
TXTEN
Transmitter Transfer Enable
8
1
read-only
RCR
Receive Counter Register
0x104
32
read-write
n
0x0
0x0
RXCTR
Receive Counter Register
0
16
read-write
RHR
Receive Holding Register
0x18
32
read-only
n
0x0
0x0
RXCHR
Received Character
0
9
read-only
RXSYNH
Received Sync
15
1
read-only
RNCR
Receive Next Counter Register
0x114
32
read-write
n
0x0
0x0
RXNCTR
Receive Next Counter
0
16
read-write
RNPR
Receive Next Pointer Register
0x110
32
read-write
n
0x0
0x0
RXNPTR
Receive Next Pointer
0
32
read-write
RPR
Receive Pointer Register
0x100
32
read-write
n
0x0
0x0
RXPTR
Receive Pointer Register
0
32
read-write
RTOR
Receiver Time-out Register
0x24
32
read-write
n
0x0
0x0
TO
Time-out Value
0
16
read-write
TCR
Transmit Counter Register
0x10C
32
read-write
n
0x0
0x0
TXCTR
Transmit Counter Register
0
16
read-write
THR
Transmit Holding Register
0x1C
32
write-only
n
0x0
0x0
TXCHR
Character to be Transmitted
0
9
write-only
TXSYNH
Sync Field to be Transmitted
15
1
write-only
TNCR
Transmit Next Counter Register
0x11C
32
read-write
n
0x0
0x0
TXNCTR
Transmit Counter Next
0
16
read-write
TNPR
Transmit Next Pointer Register
0x118
32
read-write
n
0x0
0x0
TXNPTR
Transmit Next Pointer
0
32
read-write
TPR
Transmit Pointer Register
0x108
32
read-write
n
0x0
0x0
TXPTR
Transmit Counter Register
0
32
read-write
TTGR
Transmitter Timeguard Register
0x28
32
read-write
n
0x0
0x0
TG
Timeguard Value
0
8
read-write
WPMR
Write Protection Mode Register
0xE4
32
read-write
n
0x0
0x0
WPEN
Write Protection Enable
0
1
read-write
WPKEY
Write Protection Key
8
24
read-write
PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.
0x555341
WPSR
Write Protection Status Register
0xE8
32
read-only
n
0x0
0x0
WPVS
Write Protection Violation Status
0
1
read-only
WPVSRC
Write Protection Violation Source
8
16
read-only
WDT
Watchdog Timer
SYSC
0x0
0x0
0x200
registers
n
CR
Control Register
0x0
32
write-only
n
0x0
0x0
KEY
Password.
24
8
write-only
PASSWD
Writing any other value in this field aborts the write operation.
0xA5
WDRSTT
Watchdog Restart
0
1
write-only
MR
Mode Register
0x4
32
read-write
n
0x0
0x0
WDD
Watchdog Delta Value
16
12
read-write
WDDBGHLT
Watchdog Debug Halt
28
1
read-write
WDDIS
Watchdog Disable
15
1
read-write
WDFIEN
Watchdog Fault Interrupt Enable
12
1
read-write
WDIDLEHLT
Watchdog Idle Halt
29
1
read-write
WDRPROC
Watchdog Reset Processor
14
1
read-write
WDRSTEN
Watchdog Reset Enable
13
1
read-write
WDV
Watchdog Counter Value
0
12
read-write
SR
Status Register
0x8
32
read-only
n
0x0
0x0
WDERR
Watchdog Error
1
1
read-only
WDUNF
Watchdog Underflow
0
1
read-only